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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [gdb/] [xtensa-config.c] - Blame information for rev 816

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1 227 jeremybenn 
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
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   Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010
4 
   Free Software Foundation, Inc.
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6 
   This file is part of GDB.
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8 
   This program is free software; you can redistribute it and/or modify
9 
   it under the terms of the GNU General Public License as published by
10 
   the Free Software Foundation; either version 3 of the License, or
11 
   (at your option) any later version.
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13 
   This program is distributed in the hope that it will be useful,
14 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#define XTENSA_CONFIG_VERSION 0x60
22 
 
23 
#include "xtensa-config.h"
24 
#include "xtensa-tdep.h"
25 
 
26 
 
27 
 
28 
/* Masked registers.  */
29 
xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
30 
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
31 
xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
32 
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
33 
xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
34 
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
35 
xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
36 
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
37 
xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
38 
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
39 
xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
40 
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
41 
xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
42 
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
43 
xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
44 
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
45 
xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
46 
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
47 
xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
48 
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
49 
xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
50 
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
51 
xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
52 
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
53 
xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
54 
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
55 
xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
56 
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
57 
xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
58 
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
59 
xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
60 
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
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62 
 
63 
/* Register map.  */
64 
xtensa_register_t rmap[] =
65 
{
66 
  /*    idx ofs bi sz al targno  flags cp typ group name  */
67 
  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc,          0,0,0,0,0,0)
68 
  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,         0,0,0,0,0,0)
69 
  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,         0,0,0,0,0,0)
70 
  XTREG(  3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2,         0,0,0,0,0,0)
71 
  XTREG(  4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3,         0,0,0,0,0,0)
72 
  XTREG(  5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4,         0,0,0,0,0,0)
73 
  XTREG(  6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5,         0,0,0,0,0,0)
74 
  XTREG(  7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6,         0,0,0,0,0,0)
75 
  XTREG(  8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7,         0,0,0,0,0,0)
76 
  XTREG(  9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8,         0,0,0,0,0,0)
77 
  XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9,         0,0,0,0,0,0)
78 
  XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10,        0,0,0,0,0,0)
79 
  XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11,        0,0,0,0,0,0)
80 
  XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12,        0,0,0,0,0,0)
81 
  XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13,        0,0,0,0,0,0)
82 
  XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14,        0,0,0,0,0,0)
83 
  XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15,        0,0,0,0,0,0)
84 
  XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16,        0,0,0,0,0,0)
85 
  XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17,        0,0,0,0,0,0)
86 
  XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18,        0,0,0,0,0,0)
87 
  XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19,        0,0,0,0,0,0)
88 
  XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20,        0,0,0,0,0,0)
89 
  XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21,        0,0,0,0,0,0)
90 
  XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22,        0,0,0,0,0,0)
91 
  XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23,        0,0,0,0,0,0)
92 
  XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24,        0,0,0,0,0,0)
93 
  XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25,        0,0,0,0,0,0)
94 
  XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26,        0,0,0,0,0,0)
95 
  XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27,        0,0,0,0,0,0)
96 
  XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28,        0,0,0,0,0,0)
97 
  XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29,        0,0,0,0,0,0)
98 
  XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30,        0,0,0,0,0,0)
99 
  XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31,        0,0,0,0,0,0)
100 
  XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg,        0,0,0,0,0,0)
101 
  XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend,        0,0,0,0,0,0)
102 
  XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount,      0,0,0,0,0,0)
103 
  XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar,         0,0,0,0,0,0)
104 
  XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase,     0,0,0,0,0,0)
105 
  XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase,  0,0,0,0,0,0)
106 
  XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
107 
  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176,       0,0,0,0,0,0)
108 
  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208,       0,0,0,0,0,0)
109 
  XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,          0,0,0,0,0,0)
110 
  XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,   0,0,0,0,0,0)
111 
  XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1,   0,0,0,0,0,0)
112 
  XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr,    0,0,0,0,0,0)
113 
  XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid,        0,0,0,0,0,0)
114 
  XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid,       0,0,0,0,0,0)
115 
  XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg,     0,0,0,0,0,0)
116 
  XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg,     0,0,0,0,0,0)
117 
  XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
118 
  XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr,         0,0,0,0,0,0)
119 
  XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0,    0,0,0,0,0,0)
120 
  XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1,    0,0,0,0,0,0)
121 
  XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0,    0,0,0,0,0,0)
122 
  XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1,    0,0,0,0,0,0)
123 
  XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0,    0,0,0,0,0,0)
124 
  XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1,    0,0,0,0,0,0)
125 
  XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1,        0,0,0,0,0,0)
126 
  XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2,        0,0,0,0,0,0)
127 
  XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3,        0,0,0,0,0,0)
128 
  XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4,        0,0,0,0,0,0)
129 
  XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5,        0,0,0,0,0,0)
130 
  XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6,        0,0,0,0,0,0)
131 
  XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7,        0,0,0,0,0,0)
132 
  XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc,        0,0,0,0,0,0)
133 
  XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2,        0,0,0,0,0,0)
134 
  XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3,        0,0,0,0,0,0)
135 
  XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4,        0,0,0,0,0,0)
136 
  XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5,        0,0,0,0,0,0)
137 
  XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6,        0,0,0,0,0,0)
138 
  XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7,        0,0,0,0,0,0)
139 
  XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1,    0,0,0,0,0,0)
140 
  XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2,    0,0,0,0,0,0)
141 
  XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3,    0,0,0,0,0,0)
142 
  XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4,    0,0,0,0,0,0)
143 
  XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5,    0,0,0,0,0,0)
144 
  XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6,    0,0,0,0,0,0)
145 
  XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7,    0,0,0,0,0,0)
146 
  XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable,    0,0,0,0,0,0)
147 
  XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt,   0,0,0,0,0,0)
148 
  XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset,      0,0,0,0,0,0)
149 
  XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear,    0,0,0,0,0,0)
150 
  XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable,   0,0,0,0,0,0)
151 
  XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase,     0,0,0,0,0,0)
152 
  XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause,    0,0,0,0,0,0)
153 
  XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause,  0,0,0,0,0,0)
154 
  XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount,      0,0,0,0,0,0)
155 
  XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid,        0,0,0,0,0,0)
156 
  XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount,      0,0,0,0,0,0)
157 
  XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
158 
  XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr,    0,0,0,0,0,0)
159 
  XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0,   0,0,0,0,0,0)
160 
  XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1,   0,0,0,0,0,0)
161 
  XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2,   0,0,0,0,0,0)
162 
  XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0,       0,0,0,0,0,0)
163 
  XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1,       0,0,0,0,0,0)
164 
  XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0,          0,0,0,0,0,0)
165 
  XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1,          0,0,0,0,0,0)
166 
  XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2,          0,0,0,0,0,0)
167 
  XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3,          0,0,0,0,0,0)
168 
  XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4,          0,0,0,0,0,0)
169 
  XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5,          0,0,0,0,0,0)
170 
  XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6,          0,0,0,0,0,0)
171 
  XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7,          0,0,0,0,0,0)
172 
  XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8,          0,0,0,0,0,0)
173 
  XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9,          0,0,0,0,0,0)
174 
  XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10,         0,0,0,0,0,0)
175 
  XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11,         0,0,0,0,0,0)
176 
  XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12,         0,0,0,0,0,0)
177 
  XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13,         0,0,0,0,0,0)
178 
  XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14,         0,0,0,0,0,0)
179 
  XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15,         0,0,0,0,0,0)
180 
  XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
181 
            0,0,&xtensa_mask0,0,0,0)
182 
  XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
183 
            0,0,&xtensa_mask1,0,0,0)
184 
  XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
185 
            0,0,&xtensa_mask2,0,0,0)
186 
  XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
187 
            0,0,&xtensa_mask3,0,0,0)
188 
  XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
189 
            0,0,&xtensa_mask4,0,0,0)
190 
  XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
191 
            0,0,&xtensa_mask5,0,0,0)
192 
  XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
193 
            0,0,&xtensa_mask6,0,0,0)
194 
  XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr,
195 
            0,0,&xtensa_mask7,0,0,0)
196 
  XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben,
197 
            0,0,&xtensa_mask8,0,0,0)
198 
  XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum,
199 
            0,0,&xtensa_mask9,0,0,0)
200 
  XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
201 
            0,0,&xtensa_mask10,0,0,0)
202 
  XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
203 
            0,0,&xtensa_mask11,0,0,0)
204 
  XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
205 
            0,0,&xtensa_mask12,0,0,0)
206 
  XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4,
207 
            0,0,&xtensa_mask13,0,0,0)
208 
  XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4,
209 
            0,0,&xtensa_mask14,0,0,0)
210 
  XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase,
211 
            0,0,&xtensa_mask15,0,0,0)
212 
  XTREG_END
213 
};
214 
 
215 
 
216 
 
217 
#ifdef XTENSA_CONFIG_INSTANTIATE
218 
XTENSA_CONFIG_INSTANTIATE(rmap,0)
219 
#endif
220 
 

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