OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [include/] [elf/] [m32r.h] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* M32R ELF support for BFD.
2
   Copyright 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2008
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of BFD, the Binary File Descriptor library.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 2 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software Foundation, Inc.,
19
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
20
 
21
#ifndef _ELF_M32R_H
22
#define _ELF_M32R_H
23
 
24
#include "elf/reloc-macros.h"
25
 
26
/* Relocations.  */
27
START_RELOC_NUMBERS (elf_m32r_reloc_type)
28
  RELOC_NUMBER (R_M32R_NONE, 0)
29
  /* REL relocations */
30
  RELOC_NUMBER (R_M32R_16, 1)            /* For backwards compatibility. */
31
  RELOC_NUMBER (R_M32R_32, 2)            /* For backwards compatibility. */
32
  RELOC_NUMBER (R_M32R_24, 3)            /* For backwards compatibility. */
33
  RELOC_NUMBER (R_M32R_10_PCREL, 4)      /* For backwards compatibility. */
34
  RELOC_NUMBER (R_M32R_18_PCREL, 5)      /* For backwards compatibility. */
35
  RELOC_NUMBER (R_M32R_26_PCREL, 6)      /* For backwards compatibility. */
36
  RELOC_NUMBER (R_M32R_HI16_ULO, 7)      /* For backwards compatibility. */
37
  RELOC_NUMBER (R_M32R_HI16_SLO, 8)      /* For backwards compatibility. */
38
  RELOC_NUMBER (R_M32R_LO16, 9)          /* For backwards compatibility. */
39
  RELOC_NUMBER (R_M32R_SDA16, 10)        /* For backwards compatibility. */
40
  RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */
41
  RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12)  /* For backwards compatibility. */
42
 
43
  /* RELA relocations */
44
  RELOC_NUMBER (R_M32R_16_RELA, 33)
45
  RELOC_NUMBER (R_M32R_32_RELA, 34)
46
  RELOC_NUMBER (R_M32R_24_RELA, 35)
47
  RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36)
48
  RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37)
49
  RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38)
50
  RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39)
51
  RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40)
52
  RELOC_NUMBER (R_M32R_LO16_RELA, 41)
53
  RELOC_NUMBER (R_M32R_SDA16_RELA, 42)
54
  RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43)
55
  RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44)
56
 
57
  RELOC_NUMBER (R_M32R_REL32, 45)
58
 
59
  RELOC_NUMBER (R_M32R_GOT24, 48)
60
  RELOC_NUMBER (R_M32R_26_PLTREL, 49)
61
  RELOC_NUMBER (R_M32R_COPY, 50)
62
  RELOC_NUMBER (R_M32R_GLOB_DAT, 51)
63
  RELOC_NUMBER (R_M32R_JMP_SLOT, 52)
64
  RELOC_NUMBER (R_M32R_RELATIVE, 53)
65
  RELOC_NUMBER (R_M32R_GOTOFF, 54)
66
  RELOC_NUMBER (R_M32R_GOTPC24, 55)
67
  RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56)
68
  RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57)
69
  RELOC_NUMBER (R_M32R_GOT16_LO, 58)
70
  RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59)
71
  RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60)
72
  RELOC_NUMBER (R_M32R_GOTPC_LO, 61)
73
  RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62)
74
  RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63)
75
  RELOC_NUMBER (R_M32R_GOTOFF_LO, 64)
76
 
77
END_RELOC_NUMBERS (R_M32R_max)
78
 
79
/* Processor specific section indices.  These sections do not actually
80
   exist.  Symbols with a st_shndx field corresponding to one of these
81
   values have a special meaning.  */
82
 
83
/* Small common symbol.  */
84
#define SHN_M32R_SCOMMON        SHN_LORESERVE
85
 
86
/* Processor specific section flags.  */
87
 
88
/* This section contains sufficient relocs to be relaxed.
89
   When relaxing, even relocs of branch instructions the assembler could
90
   complete must be present because relaxing may cause the branch target to
91
   move.  */
92
#define SHF_M32R_CAN_RELAX      0x10000000
93
 
94
/* Processor specific flags for the ELF header e_flags field.  */
95
 
96
/* Two bit m32r architecture field.  */
97
#define EF_M32R_ARCH            0x30000000
98
 
99
/* m32r code.  */
100
#define E_M32R_ARCH             0x00000000
101
/* m32rx code.  */
102
#define E_M32RX_ARCH            0x10000000
103
/* m32r2 code.  */
104
#define E_M32R2_ARCH            0x20000000
105
 
106
/* 12 bit m32r new instructions field.  */
107
#define EF_M32R_INST            0x0FFF0000
108
/* Parallel instructions.  */
109
#define E_M32R_HAS_PARALLEL     0x00010000
110
/* Hidden instructions for m32rx:
111
   jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz,
112
   sc, snc.  */
113
#define E_M32R_HAS_HIDDEN_INST  0x00020000
114
/* New bit instructions:
115
   clrpsw, setpsw, bset, bclr, btst.  */
116
#define E_M32R_HAS_BIT_INST     0x00040000
117
/* Floating point instructions.  */
118
#define E_M32R_HAS_FLOAT_INST   0x00080000
119
 
120
/* 4 bit m32r ignore to check field.  */
121
#define EF_M32R_IGNORE          0x0000000F
122
 
123
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.