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jeremybenn |
// i386 register table.
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// Copyright 2007, 2008
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// Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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| 22 |
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// Make %st first as we test for it.
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| 23 |
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st, FloatReg|FloatAcc, 0, 0, 11, 33
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| 24 |
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// 8 bit regs
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| 25 |
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al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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| 26 |
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cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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| 27 |
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dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
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| 28 |
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bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
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| 29 |
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ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
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| 30 |
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ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
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| 31 |
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dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
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| 32 |
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bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
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| 33 |
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axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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| 34 |
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cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
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| 35 |
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dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
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| 36 |
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bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
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| 37 |
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spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
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| 38 |
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bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
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| 39 |
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sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
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| 40 |
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dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
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| 41 |
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r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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| 42 |
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r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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| 43 |
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r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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| 44 |
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r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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| 45 |
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r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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| 46 |
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r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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| 47 |
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r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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| 48 |
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r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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| 49 |
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// 16 bit regs
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| 50 |
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ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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| 51 |
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cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
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| 52 |
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dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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| 53 |
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bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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| 54 |
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sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
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| 55 |
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bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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| 56 |
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si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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| 57 |
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di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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| 58 |
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r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
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| 59 |
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r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
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| 60 |
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r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
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| 61 |
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r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
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| 62 |
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r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
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| 63 |
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r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
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| 64 |
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r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
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| 65 |
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r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
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| 66 |
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// 32 bit regs
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| 67 |
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
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| 68 |
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ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
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| 69 |
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edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
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| 70 |
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ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
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| 71 |
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esp, Reg32, 0, 4, 4, Dw2Inval
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| 72 |
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ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
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| 73 |
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esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
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| 74 |
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edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
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| 75 |
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r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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| 76 |
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r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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| 77 |
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r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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| 78 |
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r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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| 79 |
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r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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| 80 |
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r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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| 81 |
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r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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| 82 |
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r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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| 83 |
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
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| 84 |
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rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
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| 85 |
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rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
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| 86 |
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rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
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| 87 |
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rsp, Reg64, 0, 4, Dw2Inval, 7
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| 88 |
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rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
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| 89 |
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rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
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| 90 |
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rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
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| 91 |
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r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
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| 92 |
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r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
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| 93 |
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r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
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| 94 |
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r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
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| 95 |
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r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
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| 96 |
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r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
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| 97 |
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r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
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| 98 |
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r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
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| 99 |
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// Segment registers.
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| 100 |
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es, SReg2, 0, 0, 40, 50
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| 101 |
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cs, SReg2, 0, 1, 41, 51
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| 102 |
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ss, SReg2, 0, 2, 42, 52
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| 103 |
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ds, SReg2, 0, 3, 43, 53
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| 104 |
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fs, SReg3, 0, 4, 44, 54
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| 105 |
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gs, SReg3, 0, 5, 45, 55
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| 106 |
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flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
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| 107 |
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// Control registers.
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cr0, Control, 0, 0, Dw2Inval, Dw2Inval
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| 109 |
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cr1, Control, 0, 1, Dw2Inval, Dw2Inval
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| 110 |
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cr2, Control, 0, 2, Dw2Inval, Dw2Inval
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| 111 |
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cr3, Control, 0, 3, Dw2Inval, Dw2Inval
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| 112 |
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cr4, Control, 0, 4, Dw2Inval, Dw2Inval
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| 113 |
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cr5, Control, 0, 5, Dw2Inval, Dw2Inval
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| 114 |
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cr6, Control, 0, 6, Dw2Inval, Dw2Inval
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| 115 |
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cr7, Control, 0, 7, Dw2Inval, Dw2Inval
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| 116 |
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cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
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| 117 |
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cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
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| 118 |
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cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
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| 119 |
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cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
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| 120 |
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cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
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| 121 |
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cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
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| 122 |
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cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
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| 123 |
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cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
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| 124 |
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// Debug registers.
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db0, Debug, 0, 0, Dw2Inval, Dw2Inval
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| 126 |
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db1, Debug, 0, 1, Dw2Inval, Dw2Inval
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| 127 |
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db2, Debug, 0, 2, Dw2Inval, Dw2Inval
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| 128 |
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db3, Debug, 0, 3, Dw2Inval, Dw2Inval
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| 129 |
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db4, Debug, 0, 4, Dw2Inval, Dw2Inval
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| 130 |
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db5, Debug, 0, 5, Dw2Inval, Dw2Inval
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| 131 |
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db6, Debug, 0, 6, Dw2Inval, Dw2Inval
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| 132 |
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db7, Debug, 0, 7, Dw2Inval, Dw2Inval
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| 133 |
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db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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| 134 |
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db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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| 135 |
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db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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| 136 |
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db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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| 137 |
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db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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| 138 |
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db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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| 139 |
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db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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| 140 |
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db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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| 141 |
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dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
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| 142 |
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dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
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| 143 |
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dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
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| 144 |
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dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
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| 145 |
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dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
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| 146 |
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dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
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| 147 |
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dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
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| 148 |
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dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
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| 149 |
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dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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| 150 |
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dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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| 151 |
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dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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| 152 |
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dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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| 153 |
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dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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| 154 |
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dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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| 155 |
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dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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| 156 |
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dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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| 157 |
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// Test registers.
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| 158 |
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tr0, Test, 0, 0, Dw2Inval, Dw2Inval
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| 159 |
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tr1, Test, 0, 1, Dw2Inval, Dw2Inval
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| 160 |
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tr2, Test, 0, 2, Dw2Inval, Dw2Inval
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| 161 |
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tr3, Test, 0, 3, Dw2Inval, Dw2Inval
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| 162 |
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tr4, Test, 0, 4, Dw2Inval, Dw2Inval
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| 163 |
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tr5, Test, 0, 5, Dw2Inval, Dw2Inval
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| 164 |
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tr6, Test, 0, 6, Dw2Inval, Dw2Inval
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| 165 |
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tr7, Test, 0, 7, Dw2Inval, Dw2Inval
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| 166 |
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// MMX and simd registers.
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| 167 |
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mm0, RegMMX, 0, 0, 29, 41
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| 168 |
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mm1, RegMMX, 0, 1, 30, 42
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| 169 |
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mm2, RegMMX, 0, 2, 31, 43
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| 170 |
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mm3, RegMMX, 0, 3, 32, 44
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| 171 |
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mm4, RegMMX, 0, 4, 33, 45
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| 172 |
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mm5, RegMMX, 0, 5, 34, 46
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| 173 |
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mm6, RegMMX, 0, 6, 35, 47
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| 174 |
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mm7, RegMMX, 0, 7, 36, 48
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| 175 |
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xmm0, RegXMM, 0, 0, 21, 17
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| 176 |
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xmm1, RegXMM, 0, 1, 22, 18
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| 177 |
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xmm2, RegXMM, 0, 2, 23, 19
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| 178 |
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xmm3, RegXMM, 0, 3, 24, 20
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| 179 |
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xmm4, RegXMM, 0, 4, 25, 21
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| 180 |
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xmm5, RegXMM, 0, 5, 26, 22
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| 181 |
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xmm6, RegXMM, 0, 6, 27, 23
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| 182 |
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xmm7, RegXMM, 0, 7, 28, 24
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| 183 |
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xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
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| 184 |
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xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
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| 185 |
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xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
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| 186 |
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xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
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| 187 |
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xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
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| 188 |
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xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
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| 189 |
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xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
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| 190 |
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xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
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| 191 |
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// AVX registers.
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| 192 |
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ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
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| 193 |
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ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
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| 194 |
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ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
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| 195 |
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ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
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| 196 |
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ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
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| 197 |
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ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
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| 198 |
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ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
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| 199 |
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ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
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| 200 |
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ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
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| 201 |
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ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
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| 202 |
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ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
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| 203 |
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ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
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| 204 |
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ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
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| 205 |
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ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
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| 206 |
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ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
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| 207 |
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ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
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| 208 |
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// No type will make these registers rejected for all purposes except
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| 209 |
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// for addressing. This saves creating one extra type for RIP/EIP.
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| 210 |
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rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
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| 211 |
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eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
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| 212 |
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// No type will make these registers rejected for all purposes except
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| 213 |
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// for addressing.
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| 214 |
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eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
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| 215 |
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riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
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| 216 |
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// fp regs.
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| 217 |
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st(0), FloatReg|FloatAcc, 0, 0, 11, 33
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| 218 |
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st(1), FloatReg, 0, 1, 12, 34
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| 219 |
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st(2), FloatReg, 0, 2, 13, 35
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| 220 |
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st(3), FloatReg, 0, 3, 14, 36
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| 221 |
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st(4), FloatReg, 0, 4, 15, 37
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| 222 |
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st(5), FloatReg, 0, 5, 16, 38
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| 223 |
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st(6), FloatReg, 0, 6, 17, 39
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| 224 |
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st(7), FloatReg, 0, 7, 18, 40
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| 225 |
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// Pseudo-register names only used in .cfi_* directives
|
| 226 |
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eflags, 0, 0, 0, 9, 49
|
| 227 |
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rflags, 0, 0, 0, Dw2Inval, 49
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| 228 |
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fs.base, 0, 0, 0, Dw2Inval, 58
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| 229 |
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gs.base, 0, 0, 0, Dw2Inval, 59
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| 230 |
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tr, 0, 0, 0, 48, 62
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| 231 |
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ldtr, 0, 0, 0, 49, 63
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| 232 |
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// st0...7 for backward compatibility
|
| 233 |
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st0, 0, 0, 0, 11, 33
|
| 234 |
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st1, 0, 0, 1, 12, 34
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| 235 |
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st2, 0, 0, 2, 13, 35
|
| 236 |
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st3, 0, 0, 3, 14, 36
|
| 237 |
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st4, 0, 0, 4, 15, 37
|
| 238 |
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st5, 0, 0, 5, 16, 38
|
| 239 |
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st6, 0, 0, 6, 17, 39
|
| 240 |
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st7, 0, 0, 7, 18, 40
|
| 241 |
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fcw, 0, 0, 0, 37, 65
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| 242 |
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fsw, 0, 0, 0, 38, 66
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| 243 |
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mxcsr, 0, 0, 0, 39, 64
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