OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [opcodes/] [iq2000-desc.c] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
/* CPU data for iq2000.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2010 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <stdio.h>
27 
#include <stdarg.h>
28 
#include "ansidecl.h"
29 
#include "bfd.h"
30 
#include "symcat.h"
31 
#include "iq2000-desc.h"
32 
#include "iq2000-opc.h"
33 
#include "opintl.h"
34 
#include "libiberty.h"
35 
#include "xregex.h"
36 
 
37 
/* Attributes.  */
38 
 
39 
static const CGEN_ATTR_ENTRY bool_attr[] =
40 
{
41 
  { "#f", 0 },
42 
  { "#t", 1 },
43 
  { 0, 0 }
44 
};
45 
 
46 
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 
{
48 
  { "base", MACH_BASE },
49 
  { "iq2000", MACH_IQ2000 },
50 
  { "iq10", MACH_IQ10 },
51 
  { "max", MACH_MAX },
52 
  { 0, 0 }
53 
};
54 
 
55 
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56 
{
57 
  { "iq2000", ISA_IQ2000 },
58 
  { "max", ISA_MAX },
59 
  { 0, 0 }
60 
};
61 
 
62 
const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] =
63 
{
64 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
65 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
66 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
67 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
68 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
69 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
70 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
71 
  { 0, 0, 0 }
72 
};
73 
 
74 
const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] =
75 
{
76 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
77 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
78 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
79 
  { "PC", &bool_attr[0], &bool_attr[0] },
80 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
81 
  { 0, 0, 0 }
82 
};
83 
 
84 
const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] =
85 
{
86 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
87 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
88 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
89 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
90 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
91 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
92 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
93 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
94 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
95 
  { 0, 0, 0 }
96 
};
97 
 
98 
const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
99 
{
100 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
101 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
102 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108 
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
109 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110 
  { "PBB", &bool_attr[0], &bool_attr[0] },
111 
  { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
112 
  { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
113 
  { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] },
114 
  { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] },
115 
  { "USES-RD", &bool_attr[0], &bool_attr[0] },
116 
  { "USES-RS", &bool_attr[0], &bool_attr[0] },
117 
  { "USES-RT", &bool_attr[0], &bool_attr[0] },
118 
  { "USES-R31", &bool_attr[0], &bool_attr[0] },
119 
  { 0, 0, 0 }
120 
};
121 
 
122 
/* Instruction set variants.  */
123 
 
124 
static const CGEN_ISA iq2000_cgen_isa_table[] = {
125 
  { "iq2000", 32, 32, 32, 32 },
126 
  { 0, 0, 0, 0, 0 }
127 
};
128 
 
129 
/* Machine variants.  */
130 
 
131 
static const CGEN_MACH iq2000_cgen_mach_table[] = {
132 
  { "iq2000", "iq2000", MACH_IQ2000, 0 },
133 
  { "iq10", "iq10", MACH_IQ10, 0 },
134 
  { 0, 0, 0, 0 }
135 
};
136 
 
137 
static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] =
138 
{
139 
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
140 
  { "%0", 0, {0, {{{0, 0}}}}, 0, 0 },
141 
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
142 
  { "%1", 1, {0, {{{0, 0}}}}, 0, 0 },
143 
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
144 
  { "%2", 2, {0, {{{0, 0}}}}, 0, 0 },
145 
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
146 
  { "%3", 3, {0, {{{0, 0}}}}, 0, 0 },
147 
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
148 
  { "%4", 4, {0, {{{0, 0}}}}, 0, 0 },
149 
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
150 
  { "%5", 5, {0, {{{0, 0}}}}, 0, 0 },
151 
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
152 
  { "%6", 6, {0, {{{0, 0}}}}, 0, 0 },
153 
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
154 
  { "%7", 7, {0, {{{0, 0}}}}, 0, 0 },
155 
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
156 
  { "%8", 8, {0, {{{0, 0}}}}, 0, 0 },
157 
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
158 
  { "%9", 9, {0, {{{0, 0}}}}, 0, 0 },
159 
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
160 
  { "%10", 10, {0, {{{0, 0}}}}, 0, 0 },
161 
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
162 
  { "%11", 11, {0, {{{0, 0}}}}, 0, 0 },
163 
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
164 
  { "%12", 12, {0, {{{0, 0}}}}, 0, 0 },
165 
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
166 
  { "%13", 13, {0, {{{0, 0}}}}, 0, 0 },
167 
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
168 
  { "%14", 14, {0, {{{0, 0}}}}, 0, 0 },
169 
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
170 
  { "%15", 15, {0, {{{0, 0}}}}, 0, 0 },
171 
  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
172 
  { "%16", 16, {0, {{{0, 0}}}}, 0, 0 },
173 
  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
174 
  { "%17", 17, {0, {{{0, 0}}}}, 0, 0 },
175 
  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
176 
  { "%18", 18, {0, {{{0, 0}}}}, 0, 0 },
177 
  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
178 
  { "%19", 19, {0, {{{0, 0}}}}, 0, 0 },
179 
  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
180 
  { "%20", 20, {0, {{{0, 0}}}}, 0, 0 },
181 
  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
182 
  { "%21", 21, {0, {{{0, 0}}}}, 0, 0 },
183 
  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
184 
  { "%22", 22, {0, {{{0, 0}}}}, 0, 0 },
185 
  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
186 
  { "%23", 23, {0, {{{0, 0}}}}, 0, 0 },
187 
  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
188 
  { "%24", 24, {0, {{{0, 0}}}}, 0, 0 },
189 
  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
190 
  { "%25", 25, {0, {{{0, 0}}}}, 0, 0 },
191 
  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
192 
  { "%26", 26, {0, {{{0, 0}}}}, 0, 0 },
193 
  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
194 
  { "%27", 27, {0, {{{0, 0}}}}, 0, 0 },
195 
  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
196 
  { "%28", 28, {0, {{{0, 0}}}}, 0, 0 },
197 
  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
198 
  { "%29", 29, {0, {{{0, 0}}}}, 0, 0 },
199 
  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
200 
  { "%30", 30, {0, {{{0, 0}}}}, 0, 0 },
201 
  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
202 
  { "%31", 31, {0, {{{0, 0}}}}, 0, 0 }
203 
};
204 
 
205 
CGEN_KEYWORD iq2000_cgen_opval_gr_names =
206 
{
207 
  & iq2000_cgen_opval_gr_names_entries[0],
208 
  64,
209 
  0, 0, 0, 0, ""
210 
};
211 
 
212 
 
213 
/* The hardware table.  */
214 
 
215 
#define A(a) (1 << CGEN_HW_##a)
216 
 
217 
const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
218 
{
219 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
220 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
221 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
222 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
223 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
224 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
225 
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
226 
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
227 
};
228 
 
229 
#undef A
230 
 
231 
 
232 
/* The instruction field table.  */
233 
 
234 
#define A(a) (1 << CGEN_IFLD_##a)
235 
 
236 
const CGEN_IFLD iq2000_cgen_ifld_table[] =
237 
{
238 
  { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
239 
  { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
240 
  { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
241 
  { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
242 
  { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
243 
  { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
244 
  { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
245 
  { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
246 
  { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
247 
  { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
248 
  { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
249 
  { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
250 
  { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
251 
  { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
252 
  { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
253 
  { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
254 
  { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
255 
  { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
256 
  { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
257 
  { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
258 
  { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
259 
  { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
260 
  { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
261 
  { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
262 
  { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
263 
  { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
264 
  { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
265 
  { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
266 
  { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
267 
  { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
268 
  { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
269 
  { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
270 
  { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
271 
  { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
272 
  { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273 
  { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274 
  { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275 
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
276 
};
277 
 
278 
#undef A
279 
 
280 
 
281 
 
282 
/* multi ifield declarations */
283 
 
284 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [];
285 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [];
286 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
287 
 
288 
 
289 
/* multi ifield definitions */
290 
 
291 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
292 
{
293 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
294 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
295 
    { 0, { (const PTR) 0 } }
296 
};
297 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
298 
{
299 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
300 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
301 
    { 0, { (const PTR) 0 } }
302 
};
303 
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
304 
{
305 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
306 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
307 
    { 0, { (const PTR) 0 } }
308 
};
309 
 
310 
/* The operand table.  */
311 
 
312 
#define A(a) (1 << CGEN_OPERAND_##a)
313 
#define OPERAND(op) IQ2000_OPERAND_##op
314 
 
315 
const CGEN_OPERAND iq2000_cgen_operand_table[] =
316 
{
317 
/* pc: program counter */
318 
  { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
319 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
320 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
321 
/* rs: register Rs */
322 
  { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
323 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
324 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
325 
/* rt: register Rt */
326 
  { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
327 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
328 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
329 
/* rd: register Rd */
330 
  { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
331 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
332 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
333 
/* rd-rs: register Rd from Rs */
334 
  { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
335 
    { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
336 
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
337 
/* rd-rt: register Rd from Rt */
338 
  { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
339 
    { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
340 
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
341 
/* rt-rs: register Rt from Rs */
342 
  { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
343 
    { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
344 
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
345 
/* shamt: shift amount */
346 
  { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
347 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
348 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
349 
/* imm: immediate */
350 
  { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
351 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
352 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
353 
/* offset: pc-relative offset */
354 
  { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
355 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
356 
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
357 
/* baseoff: base register offset */
358 
  { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
359 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
360 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
361 
/* jmptarg: jump target */
362 
  { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
363 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
364 
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
365 
/* mask: mask */
366 
  { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
367 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
368 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
369 
/* maskq10: iq10 mask */
370 
  { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
371 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
372 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
373 
/* maskl: mask left */
374 
  { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
375 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
376 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
377 
/* count: count */
378 
  { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
379 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
380 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
381 
/* _index: index */
382 
  { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
383 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
384 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
385 
/* execode: execcode */
386 
  { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
387 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
388 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
389 
/* bytecount: byte count */
390 
  { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
391 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
392 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
393 
/* cam-y: cam global opn y */
394 
  { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
395 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
396 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
397 
/* cam-z: cam global mask z */
398 
  { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
399 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
400 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
401 
/* cm-3func: CM 3 bit fn field */
402 
  { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
403 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
404 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
405 
/* cm-4func: CM 4 bit fn field */
406 
  { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
407 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
408 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
409 
/* cm-3z: CM 3 bit Z field */
410 
  { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
411 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
412 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
413 
/* cm-4z: CM 4 bit Z field */
414 
  { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
415 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
416 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
417 
/* base: base register */
418 
  { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
419 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
420 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
421 
/* maskr: mask right */
422 
  { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
423 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
424 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
425 
/* bitnum: bit number */
426 
  { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
427 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
428 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
429 
/* hi16: high 16 bit immediate */
430 
  { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
431 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
432 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
433 
/* lo16: 16 bit signed immediate, for low */
434 
  { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
435 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
436 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
437 
/* mlo16: negated 16 bit signed immediate */
438 
  { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
439 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
440 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
441 
/* jmptargq10: iq10 21-bit jump offset */
442 
  { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
443 
    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
444 
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
445 
/* sentinel */
446 
  { 0, 0, 0, 0, 0,
447 
    { 0, { (const PTR) 0 } },
448 
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
449 
};
450 
 
451 
#undef A
452 
 
453 
 
454 
/* The instruction table.  */
455 
 
456 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
457 
#define A(a) (1 << CGEN_INSN_##a)
458 
 
459 
static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
460 
{
461 
  /* Special null first entry.
462 
     A `num' value of zero is thus invalid.
463 
     Also, the special `invalid' insn resides here.  */
464 
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
465 
/* add ${rd-rs},$rt */
466 
  {
467 
    -1, "add2", "add", 32,
468 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
469 
  },
470 
/* add $rd,$rs,$rt */
471 
  {
472 
    IQ2000_INSN_ADD, "add", "add", 32,
473 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
474 
  },
475 
/* addi ${rt-rs},$lo16 */
476 
  {
477 
    -1, "addi2", "addi", 32,
478 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
479 
  },
480 
/* addi $rt,$rs,$lo16 */
481 
  {
482 
    IQ2000_INSN_ADDI, "addi", "addi", 32,
483 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
484 
  },
485 
/* addiu ${rt-rs},$lo16 */
486 
  {
487 
    -1, "addiu2", "addiu", 32,
488 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
489 
  },
490 
/* addiu $rt,$rs,$lo16 */
491 
  {
492 
    IQ2000_INSN_ADDIU, "addiu", "addiu", 32,
493 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
494 
  },
495 
/* addu ${rd-rs},$rt */
496 
  {
497 
    -1, "addu2", "addu", 32,
498 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
499 
  },
500 
/* addu $rd,$rs,$rt */
501 
  {
502 
    IQ2000_INSN_ADDU, "addu", "addu", 32,
503 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
504 
  },
505 
/* ado16 ${rd-rs},$rt */
506 
  {
507 
    -1, "ado162", "ado16", 32,
508 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
509 
  },
510 
/* ado16 $rd,$rs,$rt */
511 
  {
512 
    IQ2000_INSN_ADO16, "ado16", "ado16", 32,
513 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
514 
  },
515 
/* and ${rd-rs},$rt */
516 
  {
517 
    -1, "and2", "and", 32,
518 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
519 
  },
520 
/* and $rd,$rs,$rt */
521 
  {
522 
    IQ2000_INSN_AND, "and", "and", 32,
523 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
524 
  },
525 
/* andi ${rt-rs},$lo16 */
526 
  {
527 
    -1, "andi2", "andi", 32,
528 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
529 
  },
530 
/* andi $rt,$rs,$lo16 */
531 
  {
532 
    IQ2000_INSN_ANDI, "andi", "andi", 32,
533 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
534 
  },
535 
/* andoi ${rt-rs},$lo16 */
536 
  {
537 
    -1, "andoi2", "andoi", 32,
538 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
539 
  },
540 
/* andoi $rt,$rs,$lo16 */
541 
  {
542 
    IQ2000_INSN_ANDOI, "andoi", "andoi", 32,
543 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
544 
  },
545 
/* nor ${rd-rs},$rt */
546 
  {
547 
    -1, "nor2", "nor", 32,
548 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
549 
  },
550 
/* nor $rd,$rs,$rt */
551 
  {
552 
    IQ2000_INSN_NOR, "nor", "nor", 32,
553 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
554 
  },
555 
/* or ${rd-rs},$rt */
556 
  {
557 
    -1, "or2", "or", 32,
558 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
559 
  },
560 
/* or $rd,$rs,$rt */
561 
  {
562 
    IQ2000_INSN_OR, "or", "or", 32,
563 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
564 
  },
565 
/* ori ${rt-rs},$lo16 */
566 
  {
567 
    -1, "ori2", "ori", 32,
568 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
569 
  },
570 
/* ori $rt,$rs,$lo16 */
571 
  {
572 
    IQ2000_INSN_ORI, "ori", "ori", 32,
573 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
574 
  },
575 
/* ram $rd,$rt,$shamt,$maskl,$maskr */
576 
  {
577 
    IQ2000_INSN_RAM, "ram", "ram", 32,
578 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
579 
  },
580 
/* sll $rd,$rt,$shamt */
581 
  {
582 
    IQ2000_INSN_SLL, "sll", "sll", 32,
583 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
584 
  },
585 
/* sllv ${rd-rt},$rs */
586 
  {
587 
    -1, "sllv2", "sllv", 32,
588 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
589 
  },
590 
/* sllv $rd,$rt,$rs */
591 
  {
592 
    IQ2000_INSN_SLLV, "sllv", "sllv", 32,
593 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
594 
  },
595 
/* slmv ${rd-rt},$rs,$shamt */
596 
  {
597 
    -1, "slmv2", "slmv", 32,
598 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
599 
  },
600 
/* slmv $rd,$rt,$rs,$shamt */
601 
  {
602 
    IQ2000_INSN_SLMV, "slmv", "slmv", 32,
603 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
604 
  },
605 
/* slt ${rd-rs},$rt */
606 
  {
607 
    -1, "slt2", "slt", 32,
608 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
609 
  },
610 
/* slt $rd,$rs,$rt */
611 
  {
612 
    IQ2000_INSN_SLT, "slt", "slt", 32,
613 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
614 
  },
615 
/* slti ${rt-rs},$imm */
616 
  {
617 
    -1, "slti2", "slti", 32,
618 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
619 
  },
620 
/* slti $rt,$rs,$imm */
621 
  {
622 
    IQ2000_INSN_SLTI, "slti", "slti", 32,
623 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
624 
  },
625 
/* sltiu ${rt-rs},$imm */
626 
  {
627 
    -1, "sltiu2", "sltiu", 32,
628 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
629 
  },
630 
/* sltiu $rt,$rs,$imm */
631 
  {
632 
    IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32,
633 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
634 
  },
635 
/* sltu ${rd-rs},$rt */
636 
  {
637 
    -1, "sltu2", "sltu", 32,
638 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
639 
  },
640 
/* sltu $rd,$rs,$rt */
641 
  {
642 
    IQ2000_INSN_SLTU, "sltu", "sltu", 32,
643 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
644 
  },
645 
/* sra ${rd-rt},$shamt */
646 
  {
647 
    -1, "sra2", "sra", 32,
648 
    { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
649 
  },
650 
/* sra $rd,$rt,$shamt */
651 
  {
652 
    IQ2000_INSN_SRA, "sra", "sra", 32,
653 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
654 
  },
655 
/* srav ${rd-rt},$rs */
656 
  {
657 
    -1, "srav2", "srav", 32,
658 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
659 
  },
660 
/* srav $rd,$rt,$rs */
661 
  {
662 
    IQ2000_INSN_SRAV, "srav", "srav", 32,
663 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
664 
  },
665 
/* srl $rd,$rt,$shamt */
666 
  {
667 
    IQ2000_INSN_SRL, "srl", "srl", 32,
668 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
669 
  },
670 
/* srlv ${rd-rt},$rs */
671 
  {
672 
    -1, "srlv2", "srlv", 32,
673 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
674 
  },
675 
/* srlv $rd,$rt,$rs */
676 
  {
677 
    IQ2000_INSN_SRLV, "srlv", "srlv", 32,
678 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
679 
  },
680 
/* srmv ${rd-rt},$rs,$shamt */
681 
  {
682 
    -1, "srmv2", "srmv", 32,
683 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
684 
  },
685 
/* srmv $rd,$rt,$rs,$shamt */
686 
  {
687 
    IQ2000_INSN_SRMV, "srmv", "srmv", 32,
688 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
689 
  },
690 
/* sub ${rd-rs},$rt */
691 
  {
692 
    -1, "sub2", "sub", 32,
693 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
694 
  },
695 
/* sub $rd,$rs,$rt */
696 
  {
697 
    IQ2000_INSN_SUB, "sub", "sub", 32,
698 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
699 
  },
700 
/* subu ${rd-rs},$rt */
701 
  {
702 
    -1, "subu2", "subu", 32,
703 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
704 
  },
705 
/* subu $rd,$rs,$rt */
706 
  {
707 
    IQ2000_INSN_SUBU, "subu", "subu", 32,
708 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
709 
  },
710 
/* xor ${rd-rs},$rt */
711 
  {
712 
    -1, "xor2", "xor", 32,
713 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
714 
  },
715 
/* xor $rd,$rs,$rt */
716 
  {
717 
    IQ2000_INSN_XOR, "xor", "xor", 32,
718 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
719 
  },
720 
/* xori ${rt-rs},$lo16 */
721 
  {
722 
    -1, "xori2", "xori", 32,
723 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
724 
  },
725 
/* xori $rt,$rs,$lo16 */
726 
  {
727 
    IQ2000_INSN_XORI, "xori", "xori", 32,
728 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
729 
  },
730 
/* bbi $rs($bitnum),$offset */
731 
  {
732 
    IQ2000_INSN_BBI, "bbi", "bbi", 32,
733 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
734 
  },
735 
/* bbin $rs($bitnum),$offset */
736 
  {
737 
    IQ2000_INSN_BBIN, "bbin", "bbin", 32,
738 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
739 
  },
740 
/* bbv $rs,$rt,$offset */
741 
  {
742 
    IQ2000_INSN_BBV, "bbv", "bbv", 32,
743 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
744 
  },
745 
/* bbvn $rs,$rt,$offset */
746 
  {
747 
    IQ2000_INSN_BBVN, "bbvn", "bbvn", 32,
748 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
749 
  },
750 
/* beq $rs,$rt,$offset */
751 
  {
752 
    IQ2000_INSN_BEQ, "beq", "beq", 32,
753 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
754 
  },
755 
/* beql $rs,$rt,$offset */
756 
  {
757 
    IQ2000_INSN_BEQL, "beql", "beql", 32,
758 
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
759 
  },
760 
/* bgez $rs,$offset */
761 
  {
762 
    IQ2000_INSN_BGEZ, "bgez", "bgez", 32,
763 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
764 
  },
765 
/* bgezal $rs,$offset */
766 
  {
767 
    IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32,
768 
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
769 
  },
770 
/* bgezall $rs,$offset */
771 
  {
772 
    IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32,
773 
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
774 
  },
775 
/* bgezl $rs,$offset */
776 
  {
777 
    IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32,
778 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
779 
  },
780 
/* bltz $rs,$offset */
781 
  {
782 
    IQ2000_INSN_BLTZ, "bltz", "bltz", 32,
783 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
784 
  },
785 
/* bltzl $rs,$offset */
786 
  {
787 
    IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32,
788 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
789 
  },
790 
/* bltzal $rs,$offset */
791 
  {
792 
    IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32,
793 
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
794 
  },
795 
/* bltzall $rs,$offset */
796 
  {
797 
    IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32,
798 
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
799 
  },
800 
/* bmb0 $rs,$rt,$offset */
801 
  {
802 
    IQ2000_INSN_BMB0, "bmb0", "bmb0", 32,
803 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
804 
  },
805 
/* bmb1 $rs,$rt,$offset */
806 
  {
807 
    IQ2000_INSN_BMB1, "bmb1", "bmb1", 32,
808 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
809 
  },
810 
/* bmb2 $rs,$rt,$offset */
811 
  {
812 
    IQ2000_INSN_BMB2, "bmb2", "bmb2", 32,
813 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
814 
  },
815 
/* bmb3 $rs,$rt,$offset */
816 
  {
817 
    IQ2000_INSN_BMB3, "bmb3", "bmb3", 32,
818 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
819 
  },
820 
/* bne $rs,$rt,$offset */
821 
  {
822 
    IQ2000_INSN_BNE, "bne", "bne", 32,
823 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
824 
  },
825 
/* bnel $rs,$rt,$offset */
826 
  {
827 
    IQ2000_INSN_BNEL, "bnel", "bnel", 32,
828 
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
829 
  },
830 
/* jalr $rd,$rs */
831 
  {
832 
    IQ2000_INSN_JALR, "jalr", "jalr", 32,
833 
    { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
834 
  },
835 
/* jr $rs */
836 
  {
837 
    IQ2000_INSN_JR, "jr", "jr", 32,
838 
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
839 
  },
840 
/* lb $rt,$lo16($base) */
841 
  {
842 
    IQ2000_INSN_LB, "lb", "lb", 32,
843 
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
844 
  },
845 
/* lbu $rt,$lo16($base) */
846 
  {
847 
    IQ2000_INSN_LBU, "lbu", "lbu", 32,
848 
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
849 
  },
850 
/* lh $rt,$lo16($base) */
851 
  {
852 
    IQ2000_INSN_LH, "lh", "lh", 32,
853 
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
854 
  },
855 
/* lhu $rt,$lo16($base) */
856 
  {
857 
    IQ2000_INSN_LHU, "lhu", "lhu", 32,
858 
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
859 
  },
860 
/* lui $rt,$hi16 */
861 
  {
862 
    IQ2000_INSN_LUI, "lui", "lui", 32,
863 
    { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } }
864 
  },
865 
/* lw $rt,$lo16($base) */
866 
  {
867 
    IQ2000_INSN_LW, "lw", "lw", 32,
868 
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
869 
  },
870 
/* sb $rt,$lo16($base) */
871 
  {
872 
    IQ2000_INSN_SB, "sb", "sb", 32,
873 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
874 
  },
875 
/* sh $rt,$lo16($base) */
876 
  {
877 
    IQ2000_INSN_SH, "sh", "sh", 32,
878 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
879 
  },
880 
/* sw $rt,$lo16($base) */
881 
  {
882 
    IQ2000_INSN_SW, "sw", "sw", 32,
883 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
884 
  },
885 
/* break */
886 
  {
887 
    IQ2000_INSN_BREAK, "break", "break", 32,
888 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
889 
  },
890 
/* syscall */
891 
  {
892 
    IQ2000_INSN_SYSCALL, "syscall", "syscall", 32,
893 
    { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } }
894 
  },
895 
/* andoui $rt,$rs,$hi16 */
896 
  {
897 
    IQ2000_INSN_ANDOUI, "andoui", "andoui", 32,
898 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
899 
  },
900 
/* andoui ${rt-rs},$hi16 */
901 
  {
902 
    -1, "andoui2", "andoui", 32,
903 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
904 
  },
905 
/* orui ${rt-rs},$hi16 */
906 
  {
907 
    -1, "orui2", "orui", 32,
908 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
909 
  },
910 
/* orui $rt,$rs,$hi16 */
911 
  {
912 
    IQ2000_INSN_ORUI, "orui", "orui", 32,
913 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
914 
  },
915 
/* bgtz $rs,$offset */
916 
  {
917 
    IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32,
918 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
919 
  },
920 
/* bgtzl $rs,$offset */
921 
  {
922 
    IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32,
923 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
924 
  },
925 
/* blez $rs,$offset */
926 
  {
927 
    IQ2000_INSN_BLEZ, "blez", "blez", 32,
928 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
929 
  },
930 
/* blezl $rs,$offset */
931 
  {
932 
    IQ2000_INSN_BLEZL, "blezl", "blezl", 32,
933 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
934 
  },
935 
/* mrgb $rd,$rs,$rt,$mask */
936 
  {
937 
    IQ2000_INSN_MRGB, "mrgb", "mrgb", 32,
938 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
939 
  },
940 
/* mrgb ${rd-rs},$rt,$mask */
941 
  {
942 
    -1, "mrgb2", "mrgb", 32,
943 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
944 
  },
945 
/* bctxt $rs,$offset */
946 
  {
947 
    IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32,
948 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
949 
  },
950 
/* bc0f $offset */
951 
  {
952 
    IQ2000_INSN_BC0F, "bc0f", "bc0f", 32,
953 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
954 
  },
955 
/* bc0fl $offset */
956 
  {
957 
    IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32,
958 
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
959 
  },
960 
/* bc3f $offset */
961 
  {
962 
    IQ2000_INSN_BC3F, "bc3f", "bc3f", 32,
963 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
964 
  },
965 
/* bc3fl $offset */
966 
  {
967 
    IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32,
968 
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
969 
  },
970 
/* bc0t $offset */
971 
  {
972 
    IQ2000_INSN_BC0T, "bc0t", "bc0t", 32,
973 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
974 
  },
975 
/* bc0tl $offset */
976 
  {
977 
    IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32,
978 
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
979 
  },
980 
/* bc3t $offset */
981 
  {
982 
    IQ2000_INSN_BC3T, "bc3t", "bc3t", 32,
983 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
984 
  },
985 
/* bc3tl $offset */
986 
  {
987 
    IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32,
988 
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
989 
  },
990 
/* cfc0 $rt,$rd */
991 
  {
992 
    IQ2000_INSN_CFC0, "cfc0", "cfc0", 32,
993 
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
994 
  },
995 
/* cfc1 $rt,$rd */
996 
  {
997 
    IQ2000_INSN_CFC1, "cfc1", "cfc1", 32,
998 
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
999 
  },
1000 
/* cfc2 $rt,$rd */
1001 
  {
1002 
    IQ2000_INSN_CFC2, "cfc2", "cfc2", 32,
1003 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1004 
  },
1005 
/* cfc3 $rt,$rd */
1006 
  {
1007 
    IQ2000_INSN_CFC3, "cfc3", "cfc3", 32,
1008 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1009 
  },
1010 
/* chkhdr $rd,$rt */
1011 
  {
1012 
    IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32,
1013 
    { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1014 
  },
1015 
/* ctc0 $rt,$rd */
1016 
  {
1017 
    IQ2000_INSN_CTC0, "ctc0", "ctc0", 32,
1018 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1019 
  },
1020 
/* ctc1 $rt,$rd */
1021 
  {
1022 
    IQ2000_INSN_CTC1, "ctc1", "ctc1", 32,
1023 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1024 
  },
1025 
/* ctc2 $rt,$rd */
1026 
  {
1027 
    IQ2000_INSN_CTC2, "ctc2", "ctc2", 32,
1028 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1029 
  },
1030 
/* ctc3 $rt,$rd */
1031 
  {
1032 
    IQ2000_INSN_CTC3, "ctc3", "ctc3", 32,
1033 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1034 
  },
1035 
/* jcr $rs */
1036 
  {
1037 
    IQ2000_INSN_JCR, "jcr", "jcr", 32,
1038 
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1039 
  },
1040 
/* luc32 $rt,$rd */
1041 
  {
1042 
    IQ2000_INSN_LUC32, "luc32", "luc32", 32,
1043 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1044 
  },
1045 
/* luc32l $rt,$rd */
1046 
  {
1047 
    IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32,
1048 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1049 
  },
1050 
/* luc64 $rt,$rd */
1051 
  {
1052 
    IQ2000_INSN_LUC64, "luc64", "luc64", 32,
1053 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1054 
  },
1055 
/* luc64l $rt,$rd */
1056 
  {
1057 
    IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32,
1058 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1059 
  },
1060 
/* luk $rt,$rd */
1061 
  {
1062 
    IQ2000_INSN_LUK, "luk", "luk", 32,
1063 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1064 
  },
1065 
/* lulck $rt */
1066 
  {
1067 
    IQ2000_INSN_LULCK, "lulck", "lulck", 32,
1068 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1069 
  },
1070 
/* lum32 $rt,$rd */
1071 
  {
1072 
    IQ2000_INSN_LUM32, "lum32", "lum32", 32,
1073 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1074 
  },
1075 
/* lum32l $rt,$rd */
1076 
  {
1077 
    IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32,
1078 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1079 
  },
1080 
/* lum64 $rt,$rd */
1081 
  {
1082 
    IQ2000_INSN_LUM64, "lum64", "lum64", 32,
1083 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1084 
  },
1085 
/* lum64l $rt,$rd */
1086 
  {
1087 
    IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32,
1088 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1089 
  },
1090 
/* lur $rt,$rd */
1091 
  {
1092 
    IQ2000_INSN_LUR, "lur", "lur", 32,
1093 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1094 
  },
1095 
/* lurl $rt,$rd */
1096 
  {
1097 
    IQ2000_INSN_LURL, "lurl", "lurl", 32,
1098 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1099 
  },
1100 
/* luulck $rt */
1101 
  {
1102 
    IQ2000_INSN_LUULCK, "luulck", "luulck", 32,
1103 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1104 
  },
1105 
/* mfc0 $rt,$rd */
1106 
  {
1107 
    IQ2000_INSN_MFC0, "mfc0", "mfc0", 32,
1108 
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1109 
  },
1110 
/* mfc1 $rt,$rd */
1111 
  {
1112 
    IQ2000_INSN_MFC1, "mfc1", "mfc1", 32,
1113 
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1114 
  },
1115 
/* mfc2 $rt,$rd */
1116 
  {
1117 
    IQ2000_INSN_MFC2, "mfc2", "mfc2", 32,
1118 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1119 
  },
1120 
/* mfc3 $rt,$rd */
1121 
  {
1122 
    IQ2000_INSN_MFC3, "mfc3", "mfc3", 32,
1123 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1124 
  },
1125 
/* mtc0 $rt,$rd */
1126 
  {
1127 
    IQ2000_INSN_MTC0, "mtc0", "mtc0", 32,
1128 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1129 
  },
1130 
/* mtc1 $rt,$rd */
1131 
  {
1132 
    IQ2000_INSN_MTC1, "mtc1", "mtc1", 32,
1133 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1134 
  },
1135 
/* mtc2 $rt,$rd */
1136 
  {
1137 
    IQ2000_INSN_MTC2, "mtc2", "mtc2", 32,
1138 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1139 
  },
1140 
/* mtc3 $rt,$rd */
1141 
  {
1142 
    IQ2000_INSN_MTC3, "mtc3", "mtc3", 32,
1143 
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1144 
  },
1145 
/* pkrl $rd,$rt */
1146 
  {
1147 
    IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
1148 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1149 
  },
1150 
/* pkrlr1 $rt,$_index,$count */
1151 
  {
1152 
    IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
1153 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1154 
  },
1155 
/* pkrlr30 $rt,$_index,$count */
1156 
  {
1157 
    IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
1158 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1159 
  },
1160 
/* rb $rd,$rt */
1161 
  {
1162 
    IQ2000_INSN_RB, "rb", "rb", 32,
1163 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1164 
  },
1165 
/* rbr1 $rt,$_index,$count */
1166 
  {
1167 
    IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
1168 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1169 
  },
1170 
/* rbr30 $rt,$_index,$count */
1171 
  {
1172 
    IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
1173 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1174 
  },
1175 
/* rfe */
1176 
  {
1177 
    IQ2000_INSN_RFE, "rfe", "rfe", 32,
1178 
    { 0, { { { (1<<MACH_IQ2000), 0 } } } }
1179 
  },
1180 
/* rx $rd,$rt */
1181 
  {
1182 
    IQ2000_INSN_RX, "rx", "rx", 32,
1183 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1184 
  },
1185 
/* rxr1 $rt,$_index,$count */
1186 
  {
1187 
    IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
1188 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1189 
  },
1190 
/* rxr30 $rt,$_index,$count */
1191 
  {
1192 
    IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
1193 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1194 
  },
1195 
/* sleep */
1196 
  {
1197 
    IQ2000_INSN_SLEEP, "sleep", "sleep", 32,
1198 
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1199 
  },
1200 
/* srrd $rt */
1201 
  {
1202 
    IQ2000_INSN_SRRD, "srrd", "srrd", 32,
1203 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1204 
  },
1205 
/* srrdl $rt */
1206 
  {
1207 
    IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32,
1208 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1209 
  },
1210 
/* srulck $rt */
1211 
  {
1212 
    IQ2000_INSN_SRULCK, "srulck", "srulck", 32,
1213 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1214 
  },
1215 
/* srwr $rt,$rd */
1216 
  {
1217 
    IQ2000_INSN_SRWR, "srwr", "srwr", 32,
1218 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1219 
  },
1220 
/* srwru $rt,$rd */
1221 
  {
1222 
    IQ2000_INSN_SRWRU, "srwru", "srwru", 32,
1223 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1224 
  },
1225 
/* trapqfl */
1226 
  {
1227 
    IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32,
1228 
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1229 
  },
1230 
/* trapqne */
1231 
  {
1232 
    IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32,
1233 
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1234 
  },
1235 
/* traprel $rt */
1236 
  {
1237 
    IQ2000_INSN_TRAPREL, "traprel", "traprel", 32,
1238 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1239 
  },
1240 
/* wb $rd,$rt */
1241 
  {
1242 
    IQ2000_INSN_WB, "wb", "wb", 32,
1243 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1244 
  },
1245 
/* wbu $rd,$rt */
1246 
  {
1247 
    IQ2000_INSN_WBU, "wbu", "wbu", 32,
1248 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1249 
  },
1250 
/* wbr1 $rt,$_index,$count */
1251 
  {
1252 
    IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
1253 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1254 
  },
1255 
/* wbr1u $rt,$_index,$count */
1256 
  {
1257 
    IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
1258 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1259 
  },
1260 
/* wbr30 $rt,$_index,$count */
1261 
  {
1262 
    IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
1263 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1264 
  },
1265 
/* wbr30u $rt,$_index,$count */
1266 
  {
1267 
    IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
1268 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1269 
  },
1270 
/* wx $rd,$rt */
1271 
  {
1272 
    IQ2000_INSN_WX, "wx", "wx", 32,
1273 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1274 
  },
1275 
/* wxu $rd,$rt */
1276 
  {
1277 
    IQ2000_INSN_WXU, "wxu", "wxu", 32,
1278 
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1279 
  },
1280 
/* wxr1 $rt,$_index,$count */
1281 
  {
1282 
    IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
1283 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1284 
  },
1285 
/* wxr1u $rt,$_index,$count */
1286 
  {
1287 
    IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
1288 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1289 
  },
1290 
/* wxr30 $rt,$_index,$count */
1291 
  {
1292 
    IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
1293 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1294 
  },
1295 
/* wxr30u $rt,$_index,$count */
1296 
  {
1297 
    IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
1298 
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1299 
  },
1300 
/* ldw $rt,$lo16($base) */
1301 
  {
1302 
    IQ2000_INSN_LDW, "ldw", "ldw", 32,
1303 
    { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
1304 
  },
1305 
/* sdw $rt,$lo16($base) */
1306 
  {
1307 
    IQ2000_INSN_SDW, "sdw", "sdw", 32,
1308 
    { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
1309 
  },
1310 
/* j $jmptarg */
1311 
  {
1312 
    IQ2000_INSN_J, "j", "j", 32,
1313 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1314 
  },
1315 
/* jal $jmptarg */
1316 
  {
1317 
    IQ2000_INSN_JAL, "jal", "jal", 32,
1318 
    { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1319 
  },
1320 
/* bmb $rs,$rt,$offset */
1321 
  {
1322 
    IQ2000_INSN_BMB, "bmb", "bmb", 32,
1323 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1324 
  },
1325 
/* andoui $rt,$rs,$hi16 */
1326 
  {
1327 
    IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32,
1328 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1329 
  },
1330 
/* andoui ${rt-rs},$hi16 */
1331 
  {
1332 
    -1, "andoui2-q10", "andoui", 32,
1333 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1334 
  },
1335 
/* orui $rt,$rs,$hi16 */
1336 
  {
1337 
    IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32,
1338 
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1339 
  },
1340 
/* orui ${rt-rs},$hi16 */
1341 
  {
1342 
    -1, "orui2-q10", "orui", 32,
1343 
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1344 
  },
1345 
/* mrgb $rd,$rs,$rt,$maskq10 */
1346 
  {
1347 
    IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32,
1348 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1349 
  },
1350 
/* mrgb ${rd-rs},$rt,$maskq10 */
1351 
  {
1352 
    -1, "mrgbq102", "mrgb", 32,
1353 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1354 
  },
1355 
/* j $jmptarg */
1356 
  {
1357 
    IQ2000_INSN_JQ10, "jq10", "j", 32,
1358 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1359 
  },
1360 
/* jal $rt,$jmptarg */
1361 
  {
1362 
    IQ2000_INSN_JALQ10, "jalq10", "jal", 32,
1363 
    { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1364 
  },
1365 
/* jal $jmptarg */
1366 
  {
1367 
    IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32,
1368 
    { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1369 
  },
1370 
/* bbil $rs($bitnum),$offset */
1371 
  {
1372 
    IQ2000_INSN_BBIL, "bbil", "bbil", 32,
1373 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1374 
  },
1375 
/* bbinl $rs($bitnum),$offset */
1376 
  {
1377 
    IQ2000_INSN_BBINL, "bbinl", "bbinl", 32,
1378 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1379 
  },
1380 
/* bbvl $rs,$rt,$offset */
1381 
  {
1382 
    IQ2000_INSN_BBVL, "bbvl", "bbvl", 32,
1383 
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1384 
  },
1385 
/* bbvnl $rs,$rt,$offset */
1386 
  {
1387 
    IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32,
1388 
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1389 
  },
1390 
/* bgtzal $rs,$offset */
1391 
  {
1392 
    IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32,
1393 
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1394 
  },
1395 
/* bgtzall $rs,$offset */
1396 
  {
1397 
    IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32,
1398 
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1399 
  },
1400 
/* blezal $rs,$offset */
1401 
  {
1402 
    IQ2000_INSN_BLEZAL, "blezal", "blezal", 32,
1403 
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1404 
  },
1405 
/* blezall $rs,$offset */
1406 
  {
1407 
    IQ2000_INSN_BLEZALL, "blezall", "blezall", 32,
1408 
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1409 
  },
1410 
/* bgtz $rs,$offset */
1411 
  {
1412 
    IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32,
1413 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1414 
  },
1415 
/* bgtzl $rs,$offset */
1416 
  {
1417 
    IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32,
1418 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1419 
  },
1420 
/* blez $rs,$offset */
1421 
  {
1422 
    IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32,
1423 
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1424 
  },
1425 
/* blezl $rs,$offset */
1426 
  {
1427 
    IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32,
1428 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1429 
  },
1430 
/* bmb $rs,$rt,$offset */
1431 
  {
1432 
    IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32,
1433 
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1434 
  },
1435 
/* bmbl $rs,$rt,$offset */
1436 
  {
1437 
    IQ2000_INSN_BMBL, "bmbl", "bmbl", 32,
1438 
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1439 
  },
1440 
/* bri $rs,$offset */
1441 
  {
1442 
    IQ2000_INSN_BRI, "bri", "bri", 32,
1443 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1444 
  },
1445 
/* brv $rs,$offset */
1446 
  {
1447 
    IQ2000_INSN_BRV, "brv", "brv", 32,
1448 
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1449 
  },
1450 
/* bctx $rs,$offset */
1451 
  {
1452 
    IQ2000_INSN_BCTX, "bctx", "bctx", 32,
1453 
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1454 
  },
1455 
/* yield */
1456 
  {
1457 
    IQ2000_INSN_YIELD, "yield", "yield", 32,
1458 
    { 0, { { { (1<<MACH_IQ10), 0 } } } }
1459 
  },
1460 
/* crc32 $rd,$rs,$rt */
1461 
  {
1462 
    IQ2000_INSN_CRC32, "crc32", "crc32", 32,
1463 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1464 
  },
1465 
/* crc32b $rd,$rs,$rt */
1466 
  {
1467 
    IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32,
1468 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1469 
  },
1470 
/* cnt1s $rd,$rs */
1471 
  {
1472 
    IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32,
1473 
    { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1474 
  },
1475 
/* avail $rd */
1476 
  {
1477 
    IQ2000_INSN_AVAIL, "avail", "avail", 32,
1478 
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1479 
  },
1480 
/* free $rd,$rs */
1481 
  {
1482 
    IQ2000_INSN_FREE, "free", "free", 32,
1483 
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1484 
  },
1485 
/* tstod $rd,$rs */
1486 
  {
1487 
    IQ2000_INSN_TSTOD, "tstod", "tstod", 32,
1488 
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1489 
  },
1490 
/* cmphdr $rd */
1491 
  {
1492 
    IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32,
1493 
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1494 
  },
1495 
/* mcid $rd,$rt */
1496 
  {
1497 
    IQ2000_INSN_MCID, "mcid", "mcid", 32,
1498 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1499 
  },
1500 
/* dba $rd */
1501 
  {
1502 
    IQ2000_INSN_DBA, "dba", "dba", 32,
1503 
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1504 
  },
1505 
/* dbd $rd,$rs,$rt */
1506 
  {
1507 
    IQ2000_INSN_DBD, "dbd", "dbd", 32,
1508 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1509 
  },
1510 
/* dpwt $rd,$rs */
1511 
  {
1512 
    IQ2000_INSN_DPWT, "dpwt", "dpwt", 32,
1513 
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1514 
  },
1515 
/* chkhdr $rd,$rs */
1516 
  {
1517 
    IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32,
1518 
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1519 
  },
1520 
/* rba $rd,$rs,$rt */
1521 
  {
1522 
    IQ2000_INSN_RBA, "rba", "rba", 32,
1523 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1524 
  },
1525 
/* rbal $rd,$rs,$rt */
1526 
  {
1527 
    IQ2000_INSN_RBAL, "rbal", "rbal", 32,
1528 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1529 
  },
1530 
/* rbar $rd,$rs,$rt */
1531 
  {
1532 
    IQ2000_INSN_RBAR, "rbar", "rbar", 32,
1533 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1534 
  },
1535 
/* wba $rd,$rs,$rt */
1536 
  {
1537 
    IQ2000_INSN_WBA, "wba", "wba", 32,
1538 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1539 
  },
1540 
/* wbau $rd,$rs,$rt */
1541 
  {
1542 
    IQ2000_INSN_WBAU, "wbau", "wbau", 32,
1543 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1544 
  },
1545 
/* wbac $rd,$rs,$rt */
1546 
  {
1547 
    IQ2000_INSN_WBAC, "wbac", "wbac", 32,
1548 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1549 
  },
1550 
/* rbi $rd,$rs,$rt,$bytecount */
1551 
  {
1552 
    IQ2000_INSN_RBI, "rbi", "rbi", 32,
1553 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1554 
  },
1555 
/* rbil $rd,$rs,$rt,$bytecount */
1556 
  {
1557 
    IQ2000_INSN_RBIL, "rbil", "rbil", 32,
1558 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1559 
  },
1560 
/* rbir $rd,$rs,$rt,$bytecount */
1561 
  {
1562 
    IQ2000_INSN_RBIR, "rbir", "rbir", 32,
1563 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1564 
  },
1565 
/* wbi $rd,$rs,$rt,$bytecount */
1566 
  {
1567 
    IQ2000_INSN_WBI, "wbi", "wbi", 32,
1568 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1569 
  },
1570 
/* wbic $rd,$rs,$rt,$bytecount */
1571 
  {
1572 
    IQ2000_INSN_WBIC, "wbic", "wbic", 32,
1573 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1574 
  },
1575 
/* wbiu $rd,$rs,$rt,$bytecount */
1576 
  {
1577 
    IQ2000_INSN_WBIU, "wbiu", "wbiu", 32,
1578 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1579 
  },
1580 
/* pkrli $rd,$rs,$rt,$bytecount */
1581 
  {
1582 
    IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32,
1583 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1584 
  },
1585 
/* pkrlih $rd,$rs,$rt,$bytecount */
1586 
  {
1587 
    IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32,
1588 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1589 
  },
1590 
/* pkrliu $rd,$rs,$rt,$bytecount */
1591 
  {
1592 
    IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32,
1593 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1594 
  },
1595 
/* pkrlic $rd,$rs,$rt,$bytecount */
1596 
  {
1597 
    IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32,
1598 
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1599 
  },
1600 
/* pkrla $rd,$rs,$rt */
1601 
  {
1602 
    IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32,
1603 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1604 
  },
1605 
/* pkrlau $rd,$rs,$rt */
1606 
  {
1607 
    IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32,
1608 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1609 
  },
1610 
/* pkrlah $rd,$rs,$rt */
1611 
  {
1612 
    IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32,
1613 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1614 
  },
1615 
/* pkrlac $rd,$rs,$rt */
1616 
  {
1617 
    IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32,
1618 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1619 
  },
1620 
/* lock $rd,$rt */
1621 
  {
1622 
    IQ2000_INSN_LOCK, "lock", "lock", 32,
1623 
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1624 
  },
1625 
/* unlk $rd,$rt */
1626 
  {
1627 
    IQ2000_INSN_UNLK, "unlk", "unlk", 32,
1628 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1629 
  },
1630 
/* swrd $rd,$rt */
1631 
  {
1632 
    IQ2000_INSN_SWRD, "swrd", "swrd", 32,
1633 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1634 
  },
1635 
/* swrdl $rd,$rt */
1636 
  {
1637 
    IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32,
1638 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1639 
  },
1640 
/* swwr $rd,$rs,$rt */
1641 
  {
1642 
    IQ2000_INSN_SWWR, "swwr", "swwr", 32,
1643 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1644 
  },
1645 
/* swwru $rd,$rs,$rt */
1646 
  {
1647 
    IQ2000_INSN_SWWRU, "swwru", "swwru", 32,
1648 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1649 
  },
1650 
/* dwrd $rd,$rt */
1651 
  {
1652 
    IQ2000_INSN_DWRD, "dwrd", "dwrd", 32,
1653 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1654 
  },
1655 
/* dwrdl $rd,$rt */
1656 
  {
1657 
    IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32,
1658 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1659 
  },
1660 
/* cam36 $rd,$rt,${cam-z},${cam-y} */
1661 
  {
1662 
    IQ2000_INSN_CAM36, "cam36", "cam36", 32,
1663 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1664 
  },
1665 
/* cam72 $rd,$rt,${cam-y},${cam-z} */
1666 
  {
1667 
    IQ2000_INSN_CAM72, "cam72", "cam72", 32,
1668 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1669 
  },
1670 
/* cam144 $rd,$rt,${cam-y},${cam-z} */
1671 
  {
1672 
    IQ2000_INSN_CAM144, "cam144", "cam144", 32,
1673 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1674 
  },
1675 
/* cam288 $rd,$rt,${cam-y},${cam-z} */
1676 
  {
1677 
    IQ2000_INSN_CAM288, "cam288", "cam288", 32,
1678 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1679 
  },
1680 
/* cm32and $rd,$rs,$rt */
1681 
  {
1682 
    IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32,
1683 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1684 
  },
1685 
/* cm32andn $rd,$rs,$rt */
1686 
  {
1687 
    IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32,
1688 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1689 
  },
1690 
/* cm32or $rd,$rs,$rt */
1691 
  {
1692 
    IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32,
1693 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1694 
  },
1695 
/* cm32ra $rd,$rs,$rt */
1696 
  {
1697 
    IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32,
1698 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1699 
  },
1700 
/* cm32rd $rd,$rt */
1701 
  {
1702 
    IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32,
1703 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1704 
  },
1705 
/* cm32ri $rd,$rt */
1706 
  {
1707 
    IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32,
1708 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1709 
  },
1710 
/* cm32rs $rd,$rs,$rt */
1711 
  {
1712 
    IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32,
1713 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1714 
  },
1715 
/* cm32sa $rd,$rs,$rt */
1716 
  {
1717 
    IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32,
1718 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1719 
  },
1720 
/* cm32sd $rd,$rt */
1721 
  {
1722 
    IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32,
1723 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1724 
  },
1725 
/* cm32si $rd,$rt */
1726 
  {
1727 
    IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32,
1728 
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1729 
  },
1730 
/* cm32ss $rd,$rs,$rt */
1731 
  {
1732 
    IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32,
1733 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1734 
  },
1735 
/* cm32xor $rd,$rs,$rt */
1736 
  {
1737 
    IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32,
1738 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1739 
  },
1740 
/* cm64clr $rd,$rt */
1741 
  {
1742 
    IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32,
1743 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1744 
  },
1745 
/* cm64ra $rd,$rs,$rt */
1746 
  {
1747 
    IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32,
1748 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1749 
  },
1750 
/* cm64rd $rd,$rt */
1751 
  {
1752 
    IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32,
1753 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1754 
  },
1755 
/* cm64ri $rd,$rt */
1756 
  {
1757 
    IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32,
1758 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1759 
  },
1760 
/* cm64ria2 $rd,$rs,$rt */
1761 
  {
1762 
    IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32,
1763 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1764 
  },
1765 
/* cm64rs $rd,$rs,$rt */
1766 
  {
1767 
    IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32,
1768 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1769 
  },
1770 
/* cm64sa $rd,$rs,$rt */
1771 
  {
1772 
    IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32,
1773 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1774 
  },
1775 
/* cm64sd $rd,$rt */
1776 
  {
1777 
    IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32,
1778 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1779 
  },
1780 
/* cm64si $rd,$rt */
1781 
  {
1782 
    IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32,
1783 
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1784 
  },
1785 
/* cm64sia2 $rd,$rs,$rt */
1786 
  {
1787 
    IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32,
1788 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1789 
  },
1790 
/* cm64ss $rd,$rs,$rt */
1791 
  {
1792 
    IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32,
1793 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1794 
  },
1795 
/* cm128ria2 $rd,$rs,$rt */
1796 
  {
1797 
    IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32,
1798 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1799 
  },
1800 
/* cm128ria3 $rd,$rs,$rt,${cm-3z} */
1801 
  {
1802 
    IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32,
1803 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1804 
  },
1805 
/* cm128ria4 $rd,$rs,$rt,${cm-4z} */
1806 
  {
1807 
    IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32,
1808 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1809 
  },
1810 
/* cm128sia2 $rd,$rs,$rt */
1811 
  {
1812 
    IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32,
1813 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1814 
  },
1815 
/* cm128sia3 $rd,$rs,$rt,${cm-3z} */
1816 
  {
1817 
    IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32,
1818 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1819 
  },
1820 
/* cm128sia4 $rd,$rs,$rt,${cm-4z} */
1821 
  {
1822 
    IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32,
1823 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1824 
  },
1825 
/* cm128vsa $rd,$rs,$rt */
1826 
  {
1827 
    IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32,
1828 
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1829 
  },
1830 
/* cfc $rd,$rt */
1831 
  {
1832 
    IQ2000_INSN_CFC, "cfc", "cfc", 32,
1833 
    { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } }
1834 
  },
1835 
/* ctc $rs,$rt */
1836 
  {
1837 
    IQ2000_INSN_CTC, "ctc", "ctc", 32,
1838 
    { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1839 
  },
1840 
};
1841 
 
1842 
#undef OP
1843 
#undef A
1844 
 
1845 
/* Initialize anything needed to be done once, before any cpu_open call.  */
1846 
 
1847 
static void
1848 
init_tables (void)
1849 
{
1850 
}
1851 
 
1852 
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1853 
static void build_hw_table      (CGEN_CPU_TABLE *);
1854 
static void build_ifield_table  (CGEN_CPU_TABLE *);
1855 
static void build_operand_table (CGEN_CPU_TABLE *);
1856 
static void build_insn_table    (CGEN_CPU_TABLE *);
1857 
static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1858 
 
1859 
/* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name.  */
1860 
 
1861 
static const CGEN_MACH *
1862 
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1863 
{
1864 
  while (table->name)
1865 
    {
1866 
      if (strcmp (name, table->bfd_name) == 0)
1867 
        return table;
1868 
      ++table;
1869 
    }
1870 
  abort ();
1871 
}
1872 
 
1873 
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1874 
 
1875 
static void
1876 
build_hw_table (CGEN_CPU_TABLE *cd)
1877 
{
1878 
  int i;
1879 
  int machs = cd->machs;
1880 
  const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0];
1881 
  /* MAX_HW is only an upper bound on the number of selected entries.
1882 
     However each entry is indexed by it's enum so there can be holes in
1883 
     the table.  */
1884 
  const CGEN_HW_ENTRY **selected =
1885 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1886 
 
1887 
  cd->hw_table.init_entries = init;
1888 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1889 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1890 
  /* ??? For now we just use machs to determine which ones we want.  */
1891 
  for (i = 0; init[i].name != NULL; ++i)
1892 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1893 
        & machs)
1894 
      selected[init[i].type] = &init[i];
1895 
  cd->hw_table.entries = selected;
1896 
  cd->hw_table.num_entries = MAX_HW;
1897 
}
1898 
 
1899 
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1900 
 
1901 
static void
1902 
build_ifield_table (CGEN_CPU_TABLE *cd)
1903 
{
1904 
  cd->ifld_table = & iq2000_cgen_ifld_table[0];
1905 
}
1906 
 
1907 
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1908 
 
1909 
static void
1910 
build_operand_table (CGEN_CPU_TABLE *cd)
1911 
{
1912 
  int i;
1913 
  int machs = cd->machs;
1914 
  const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0];
1915 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1916 
     However each entry is indexed by it's enum so there can be holes in
1917 
     the table.  */
1918 
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1919 
 
1920 
  cd->operand_table.init_entries = init;
1921 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1922 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1923 
  /* ??? For now we just use mach to determine which ones we want.  */
1924 
  for (i = 0; init[i].name != NULL; ++i)
1925 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1926 
        & machs)
1927 
      selected[init[i].type] = &init[i];
1928 
  cd->operand_table.entries = selected;
1929 
  cd->operand_table.num_entries = MAX_OPERANDS;
1930 
}
1931 
 
1932 
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.
1933 
   ??? This could leave out insns not supported by the specified mach/isa,
1934 
   but that would cause errors like "foo only supported by bar" to become
1935 
   "unknown insn", so for now we include all insns and require the app to
1936 
   do the checking later.
1937 
   ??? On the other hand, parsing of such insns may require their hardware or
1938 
   operand elements to be in the table [which they mightn't be].  */
1939 
 
1940 
static void
1941 
build_insn_table (CGEN_CPU_TABLE *cd)
1942 
{
1943 
  int i;
1944 
  const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
1945 
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1946 
 
1947 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1948 
  for (i = 0; i < MAX_INSNS; ++i)
1949 
    insns[i].base = &ib[i];
1950 
  cd->insn_table.init_entries = insns;
1951 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1952 
  cd->insn_table.num_init_entries = MAX_INSNS;
1953 
}
1954 
 
1955 
/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables.  */
1956 
 
1957 
static void
1958 
iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1959 
{
1960 
  int i;
1961 
  CGEN_BITSET *isas = cd->isas;
1962 
  unsigned int machs = cd->machs;
1963 
 
1964 
  cd->int_insn_p = CGEN_INT_INSN_P;
1965 
 
1966 
  /* Data derived from the isa spec.  */
1967 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1968 
  cd->default_insn_bitsize = UNSET;
1969 
  cd->base_insn_bitsize = UNSET;
1970 
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1971 
  cd->max_insn_bitsize = 0;
1972 
  for (i = 0; i < MAX_ISAS; ++i)
1973 
    if (cgen_bitset_contains (isas, i))
1974 
      {
1975 
        const CGEN_ISA *isa = & iq2000_cgen_isa_table[i];
1976 
 
1977 
        /* Default insn sizes of all selected isas must be
1978 
           equal or we set the result to 0, meaning "unknown".  */
1979 
        if (cd->default_insn_bitsize == UNSET)
1980 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1981 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1982 
          ; /* This is ok.  */
1983 
        else
1984 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1985 
 
1986 
        /* Base insn sizes of all selected isas must be equal
1987 
           or we set the result to 0, meaning "unknown".  */
1988 
        if (cd->base_insn_bitsize == UNSET)
1989 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1990 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1991 
          ; /* This is ok.  */
1992 
        else
1993 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1994 
 
1995 
        /* Set min,max insn sizes.  */
1996 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1997 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1998 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1999 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
2000 
      }
2001 
 
2002 
  /* Data derived from the mach spec.  */
2003 
  for (i = 0; i < MAX_MACHS; ++i)
2004 
    if (((1 << i) & machs) != 0)
2005 
      {
2006 
        const CGEN_MACH *mach = & iq2000_cgen_mach_table[i];
2007 
 
2008 
        if (mach->insn_chunk_bitsize != 0)
2009 
        {
2010 
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2011 
            {
2012 
              fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2013 
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2014 
              abort ();
2015 
            }
2016 
 
2017 
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2018 
        }
2019 
      }
2020 
 
2021 
  /* Determine which hw elements are used by MACH.  */
2022 
  build_hw_table (cd);
2023 
 
2024 
  /* Build the ifield table.  */
2025 
  build_ifield_table (cd);
2026 
 
2027 
  /* Determine which operands are used by MACH/ISA.  */
2028 
  build_operand_table (cd);
2029 
 
2030 
  /* Build the instruction table.  */
2031 
  build_insn_table (cd);
2032 
}
2033 
 
2034 
/* Initialize a cpu table and return a descriptor.
2035 
   It's much like opening a file, and must be the first function called.
2036 
   The arguments are a set of (type/value) pairs, terminated with
2037 
   CGEN_CPU_OPEN_END.
2038 
 
2039 
   Currently supported values:
2040 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
2041 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
2042 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2043 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
2044 
   CGEN_CPU_OPEN_END:     terminates arguments
2045 
 
2046 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2047 
   precluded.  */
2048 
 
2049 
CGEN_CPU_DESC
2050 
iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2051 
{
2052 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2053 
  static int init_p;
2054 
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
2055 
  unsigned int machs = 0; /* 0 = "unspecified" */
2056 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2057 
  va_list ap;
2058 
 
2059 
  if (! init_p)
2060 
    {
2061 
      init_tables ();
2062 
      init_p = 1;
2063 
    }
2064 
 
2065 
  memset (cd, 0, sizeof (*cd));
2066 
 
2067 
  va_start (ap, arg_type);
2068 
  while (arg_type != CGEN_CPU_OPEN_END)
2069 
    {
2070 
      switch (arg_type)
2071 
        {
2072 
        case CGEN_CPU_OPEN_ISAS :
2073 
          isas = va_arg (ap, CGEN_BITSET *);
2074 
          break;
2075 
        case CGEN_CPU_OPEN_MACHS :
2076 
          machs = va_arg (ap, unsigned int);
2077 
          break;
2078 
        case CGEN_CPU_OPEN_BFDMACH :
2079 
          {
2080 
            const char *name = va_arg (ap, const char *);
2081 
            const CGEN_MACH *mach =
2082 
              lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name);
2083 
 
2084 
            machs |= 1 << mach->num;
2085 
            break;
2086 
          }
2087 
        case CGEN_CPU_OPEN_ENDIAN :
2088 
          endian = va_arg (ap, enum cgen_endian);
2089 
          break;
2090 
        default :
2091 
          fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n",
2092 
                   arg_type);
2093 
          abort (); /* ??? return NULL? */
2094 
        }
2095 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2096 
    }
2097 
  va_end (ap);
2098 
 
2099 
  /* Mach unspecified means "all".  */
2100 
  if (machs == 0)
2101 
    machs = (1 << MAX_MACHS) - 1;
2102 
  /* Base mach is always selected.  */
2103 
  machs |= 1;
2104 
  if (endian == CGEN_ENDIAN_UNKNOWN)
2105 
    {
2106 
      /* ??? If target has only one, could have a default.  */
2107 
      fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n");
2108 
      abort ();
2109 
    }
2110 
 
2111 
  cd->isas = cgen_bitset_copy (isas);
2112 
  cd->machs = machs;
2113 
  cd->endian = endian;
2114 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
2115 
     The worry here is where both data and insn endian can be independently
2116 
     chosen, in which case this function will need another argument.
2117 
     Actually, will want to allow for more arguments in the future anyway.  */
2118 
  cd->insn_endian = endian;
2119 
 
2120 
  /* Table (re)builder.  */
2121 
  cd->rebuild_tables = iq2000_cgen_rebuild_tables;
2122 
  iq2000_cgen_rebuild_tables (cd);
2123 
 
2124 
  /* Default to not allowing signed overflow.  */
2125 
  cd->signed_overflow_ok_p = 0;
2126 
 
2127 
  return (CGEN_CPU_DESC) cd;
2128 
}
2129 
 
2130 
/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2131 
   MACH_NAME is the bfd name of the mach.  */
2132 
 
2133 
CGEN_CPU_DESC
2134 
iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2135 
{
2136 
  return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2137 
                               CGEN_CPU_OPEN_ENDIAN, endian,
2138 
                               CGEN_CPU_OPEN_END);
2139 
}
2140 
 
2141 
/* Close a cpu table.
2142 
   ??? This can live in a machine independent file, but there's currently
2143 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
2144 
   place as some simulator ports use this but they don't use libopcodes.  */
2145 
 
2146 
void
2147 
iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
2148 
{
2149 
  unsigned int i;
2150 
  const CGEN_INSN *insns;
2151 
 
2152 
  if (cd->macro_insn_table.init_entries)
2153 
    {
2154 
      insns = cd->macro_insn_table.init_entries;
2155 
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2156 
        if (CGEN_INSN_RX ((insns)))
2157 
          regfree (CGEN_INSN_RX (insns));
2158 
    }
2159 
 
2160 
  if (cd->insn_table.init_entries)
2161 
    {
2162 
      insns = cd->insn_table.init_entries;
2163 
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2164 
        if (CGEN_INSN_RX (insns))
2165 
          regfree (CGEN_INSN_RX (insns));
2166 
    }
2167 
 
2168 
  if (cd->macro_insn_table.init_entries)
2169 
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2170 
 
2171 
  if (cd->insn_table.init_entries)
2172 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
2173 
 
2174 
  if (cd->hw_table.entries)
2175 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2176 
 
2177 
  if (cd->operand_table.entries)
2178 
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2179 
 
2180 
  free (cd);
2181 
}
2182 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.