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jeremybenn |
/* Assemble Matsushita MN10200 instructions.
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Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "opcode/mn10200.h"
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const struct mn10200_operand mn10200_operands[] = {
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#define UNUSED 0
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{0, 0, 0},
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/* dn register in the first register operand position. */
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#define DN0 (UNUSED+1)
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{2, 0, MN10200_OPERAND_DREG},
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/* dn register in the second register operand position. */
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#define DN1 (DN0+1)
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{2, 2, MN10200_OPERAND_DREG},
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/* dm register in the first register operand position. */
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#define DM0 (DN1+1)
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{2, 0, MN10200_OPERAND_DREG},
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/* dm register in the second register operand position. */
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#define DM1 (DM0+1)
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{2, 2, MN10200_OPERAND_DREG},
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/* an register in the first register operand position. */
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#define AN0 (DM1+1)
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{2, 0, MN10200_OPERAND_AREG},
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/* an register in the second register operand position. */
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#define AN1 (AN0+1)
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{2, 2, MN10200_OPERAND_AREG},
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/* am register in the first register operand position. */
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#define AM0 (AN1+1)
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{2, 0, MN10200_OPERAND_AREG},
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/* am register in the second register operand position. */
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#define AM1 (AM0+1)
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{2, 2, MN10200_OPERAND_AREG},
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/* 8 bit unsigned immediate which may promote to a 16bit
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unsigned immediate. */
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#define IMM8 (AM1+1)
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{8, 0, MN10200_OPERAND_PROMOTE},
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/* 16 bit unsigned immediate which may promote to a 32bit
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unsigned immediate. */
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#define IMM16 (IMM8+1)
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{16, 0, MN10200_OPERAND_PROMOTE},
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/* 16 bit pc-relative immediate which may promote to a 16bit
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pc-relative immediate. */
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#define IMM16_PCREL (IMM16+1)
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{16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},
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/* 16bit unsigned dispacement in a memory operation which
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may promote to a 32bit displacement. */
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#define IMM16_MEM (IMM16_PCREL+1)
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{16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
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/* 24 immediate, low 16 bits in the main instruction
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word, 8 in the extension word. */
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#define IMM24 (IMM16_MEM+1)
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{24, 0, MN10200_OPERAND_EXTENDED},
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/* 32bit pc-relative offset. */
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#define IMM24_PCREL (IMM24+1)
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{24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},
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/* 32bit memory offset. */
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#define IMM24_MEM (IMM24_PCREL+1)
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{24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
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/* Processor status word. */
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#define PSW (IMM24_MEM+1)
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{0, 0, MN10200_OPERAND_PSW},
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/* MDR register. */
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#define MDR (PSW+1)
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{0, 0, MN10200_OPERAND_MDR},
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/* Index register. */
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#define DI (MDR+1)
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{2, 4, MN10200_OPERAND_DREG},
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/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
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#define SD8 (DI+1)
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{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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/* 16 bit signed displacement, may promote to 32bit dispacement. */
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#define SD16 (SD8+1)
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{16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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/* 8 bit pc-relative displacement. */
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#define SD8N_PCREL (SD16+1)
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{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},
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/* 8 bit signed immediate which may promote to 16bit signed immediate. */
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#define SIMM8 (SD8N_PCREL+1)
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{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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/* 16 bit signed immediate which may promote to 32bit immediate. */
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#define SIMM16 (SIMM8+1)
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{16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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/* 16 bit signed immediate which may not promote. */
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#define SIMM16N (SIMM16+1)
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{16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},
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/* Either an open paren or close paren. */
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#define PAREN (SIMM16N+1)
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{0, 0, MN10200_OPERAND_PAREN},
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/* dn register that appears in the first and second register positions. */
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#define DN01 (PAREN+1)
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{2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
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/* an register that appears in the first and second register positions. */
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#define AN01 (DN01+1)
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{2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
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} ;
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#define MEM(ADDR) PAREN, ADDR, PAREN
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#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
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/* The opcode table.
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The format of the opcode table is:
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NAME OPCODE MASK { OPERANDS }
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NAME is the name of the instruction.
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OPCODE is the instruction opcode.
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MASK is the opcode mask; this is used to tell the disassembler
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which bits in the actual opcode must match OPCODE.
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OPERANDS is the list of operands.
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The disassembler reads the table in order and prints the first
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instruction which matches, so this table is sorted to put more
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specific instructions before more general instructions. It is also
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sorted by major opcode. */
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const struct mn10200_opcode mn10200_opcodes[] = {
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{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
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{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}},
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{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
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{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}},
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{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
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{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
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{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
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{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
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{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
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{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}},
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{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
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{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
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{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
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{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
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{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
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{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
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{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
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{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}},
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{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}},
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{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}},
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{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}},
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{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
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{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
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{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
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{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
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{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}},
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{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}},
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{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
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{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}},
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{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}},
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{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}},
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{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
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{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
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{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 208 |
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{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
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| 211 |
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{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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| 212 |
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{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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| 213 |
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| 214 |
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{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 215 |
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{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 216 |
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{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 217 |
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{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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| 218 |
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{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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| 219 |
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{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}},
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| 220 |
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{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
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| 221 |
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{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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| 222 |
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{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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| 223 |
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{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
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| 224 |
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{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
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| 225 |
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{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
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| 226 |
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| 227 |
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{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}},
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| 228 |
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{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 229 |
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{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 230 |
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{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 231 |
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{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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| 232 |
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{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
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| 233 |
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{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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| 234 |
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| 235 |
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{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}},
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| 236 |
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{ "extx", 0xb0, 0xfc, FMT_1, {DN0}},
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| 237 |
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{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}},
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| 238 |
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{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}},
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| 239 |
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{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}},
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| 240 |
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| 241 |
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{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}},
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| 242 |
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{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
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| 243 |
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{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}},
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| 244 |
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{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}},
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| 245 |
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{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
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| 246 |
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{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
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| 247 |
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{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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| 248 |
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{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
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| 249 |
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{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
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| 250 |
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{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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| 251 |
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{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}},
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| 252 |
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{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
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| 253 |
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| 254 |
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{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}},
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| 255 |
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{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
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| 256 |
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{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}},
|
| 257 |
|
|
{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}},
|
| 258 |
|
|
{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
| 259 |
|
|
{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
| 260 |
|
|
{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}},
|
| 261 |
|
|
{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
| 262 |
|
|
{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}},
|
| 263 |
|
|
|
| 264 |
|
|
{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}},
|
| 265 |
|
|
{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}},
|
| 266 |
|
|
|
| 267 |
|
|
{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}},
|
| 268 |
|
|
|
| 269 |
|
|
{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}},
|
| 270 |
|
|
{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
|
| 271 |
|
|
{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}},
|
| 272 |
|
|
{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}},
|
| 273 |
|
|
{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
|
| 274 |
|
|
{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
|
| 275 |
|
|
{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
| 276 |
|
|
{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}},
|
| 277 |
|
|
{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
| 278 |
|
|
|
| 279 |
|
|
{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}},
|
| 280 |
|
|
{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}},
|
| 281 |
|
|
{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
|
| 282 |
|
|
{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
|
| 283 |
|
|
{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}},
|
| 284 |
|
|
{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}},
|
| 285 |
|
|
{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
|
| 286 |
|
|
{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
|
| 287 |
|
|
{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}},
|
| 288 |
|
|
{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
|
| 289 |
|
|
{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}},
|
| 290 |
|
|
|
| 291 |
|
|
{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}},
|
| 292 |
|
|
{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}},
|
| 293 |
|
|
{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}},
|
| 294 |
|
|
{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}},
|
| 295 |
|
|
|
| 296 |
|
|
{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}},
|
| 297 |
|
|
{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
|
| 298 |
|
|
{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
|
| 299 |
|
|
{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
|
| 300 |
|
|
|
| 301 |
|
|
{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 302 |
|
|
{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 303 |
|
|
{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 304 |
|
|
{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 305 |
|
|
{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 306 |
|
|
{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 307 |
|
|
{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 308 |
|
|
{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 309 |
|
|
{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 310 |
|
|
{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 311 |
|
|
{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 312 |
|
|
{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 313 |
|
|
{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 314 |
|
|
{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 315 |
|
|
{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}},
|
| 316 |
|
|
|
| 317 |
|
|
{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 318 |
|
|
{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 319 |
|
|
{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 320 |
|
|
{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 321 |
|
|
{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 322 |
|
|
{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 323 |
|
|
{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 324 |
|
|
{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 325 |
|
|
{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 326 |
|
|
{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 327 |
|
|
{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 328 |
|
|
{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 329 |
|
|
{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 330 |
|
|
{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
| 331 |
|
|
|
| 332 |
|
|
{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
| 333 |
|
|
{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
| 334 |
|
|
{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
|
| 335 |
|
|
{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
| 336 |
|
|
{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
| 337 |
|
|
{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
|
| 338 |
|
|
|
| 339 |
|
|
{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}},
|
| 340 |
|
|
|
| 341 |
|
|
{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}},
|
| 342 |
|
|
{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}},
|
| 343 |
|
|
|
| 344 |
|
|
/* Extension. We need some instruction to trigger "emulated syscalls"
|
| 345 |
|
|
for our simulator. */
|
| 346 |
|
|
{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}},
|
| 347 |
|
|
|
| 348 |
|
|
/* Extension. When talking to the simulator, gdb requires some instruction
|
| 349 |
|
|
that will trigger a "breakpoint" (really just an instruction that isn't
|
| 350 |
|
|
otherwise used by the tools. This instruction must be the same size
|
| 351 |
|
|
as the smallest instruction on the target machine. In the case of the
|
| 352 |
|
|
mn10x00 the "break" instruction must be one byte. 0xff is available on
|
| 353 |
|
|
both mn10x00 architectures. */
|
| 354 |
|
|
{ "break", 0xff, 0xff, FMT_1, {UNUSED}},
|
| 355 |
|
|
|
| 356 |
|
|
{ 0, 0, 0, 0, {0}},
|
| 357 |
|
|
|
| 358 |
|
|
} ;
|
| 359 |
|
|
|
| 360 |
|
|
const int mn10200_num_opcodes =
|
| 361 |
|
|
sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
|
| 362 |
|
|
|
| 363 |
|
|
|
