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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [opcodes/] [mcore-opc.h] - Blame information for rev 842

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1 227 jeremybenn
/* Assembler instructions for Motorola's Mcore processor
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   Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc.
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   This file is part of the GNU opcodes library.
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   This library is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, write to the Free Software
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   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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   MA 02110-1301, USA.  */
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#include "ansidecl.h"
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typedef enum
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{
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  O0,    OT,   O1,   OC,   O2,    X1,    OI,    OB,
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  OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
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  RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
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  O1R1,  OMb,  OMc,  SIa,
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  MULSH, OPSR,
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  JC,    JU,   JL,   RSI,  DO21,  OB2
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}
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mcore_opclass;
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typedef struct inst
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{
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  char *         name;
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  mcore_opclass  opclass;
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  unsigned char  transfer;
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  unsigned short inst;
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}
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mcore_opcode_info;
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#ifdef DEFINE_TABLE
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const mcore_opcode_info mcore_table[] =
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{
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  { "bkpt",     O0,     0,       0x0000 },
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  { "sync",     O0,     0,       0x0001 },
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  { "rte",      O0,     1,      0x0002 },
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  { "rfe",      O0,     1,      0x0002 },
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  { "rfi",      O0,     1,      0x0003 },
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  { "stop",     O0,     0,       0x0004 },
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  { "wait",     O0,     0,       0x0005 },
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  { "doze",     O0,     0,       0x0006 },
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  { "idly4",    O0,     0,      0x0007 },
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  { "trap",     OT,     0,       0x0008 },
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/* SPACE:                       0x000C - 0x000F */
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/* SPACE:                       0x0010 - 0x001F */
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  { "mvc",      O1,     0,       0x0020 },
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  { "mvcv",     O1,     0,       0x0030 },
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  { "ldq",      RQ,     0,       0x0040 },
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  { "stq",      RQ,     0,       0x0050 },
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  { "ldm",      RM,     0,       0x0060 },
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  { "stm",      RM,     0,       0x0070 },
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  { "dect",     O1,     0,       0x0080 },
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  { "decf",     O1,     0,       0x0090 },
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  { "inct",     O1,     0,       0x00A0 },
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  { "incf",     O1,     0,       0x00B0 },
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  { "jmp",      JMP,    2,      0x00C0 },
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#define MCORE_INST_JMP  0x00C0
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  { "jsr",      JSR,    0,       0x00D0 },
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#define MCORE_INST_JSR  0x00E0
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  { "ff1",      O1,     0,       0x00E0 },
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  { "brev",     O1,     0,       0x00F0 },
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  { "xtrb3",    X1,     0,       0x0100 },
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  { "xtrb2",    X1,     0,       0x0110 },
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  { "xtrb1",    X1,     0,       0x0120 },
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  { "xtrb0",    X1,     0,       0x0130 },
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  { "zextb",    O1,     0,       0x0140 },
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  { "sextb",    O1,     0,       0x0150 },
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  { "zexth",    O1,     0,       0x0160 },
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  { "sexth",    O1,     0,       0x0170 },
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  { "declt",    O1,     0,       0x0180 },
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  { "tstnbz",   O1,     0,       0x0190 },
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  { "decgt",    O1,     0,       0x01A0 },
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  { "decne",    O1,     0,       0x01B0 },
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  { "clrt",     O1,     0,       0x01C0 },
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  { "clrf",     O1,     0,       0x01D0 },
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  { "abs",      O1,     0,       0x01E0 },
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  { "not",      O1,     0,       0x01F0 },
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  { "movt",     O2,     0,       0x0200 },
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  { "mult",     O2,     0,       0x0300 },
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  { "loopt",    BL,     0,       0x0400 },
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  { "subu",     O2,     0,       0x0500 },
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  { "sub",      O2,     0,       0x0500 }, /* Official alias.  */
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  { "addc",     O2,     0,       0x0600 },
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  { "subc",     O2,     0,       0x0700 },
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/* SPACE: 0x0800-0x08ff for a diadic operation */
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/* SPACE: 0x0900-0x09ff for a diadic operation */
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  { "movf",     O2,     0,       0x0A00 },
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  { "lsr",      O2,     0,       0x0B00 },
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  { "cmphs",    O2,     0,       0x0C00 },
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  { "cmplt",    O2,     0,       0x0D00 },
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  { "tst",      O2,     0,       0x0E00 },
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  { "cmpne",    O2,     0,       0x0F00 },
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  { "mfcr",     OC,     0,       0x1000 },
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  { "psrclr",   OPSR,   0,       0x11F0 },
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  { "psrset",   OPSR,   0,       0x11F8 },
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  { "mov",      O2,     0,       0x1200 },
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  { "bgenr",    O2,     0,       0x1300 },
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  { "rsub",     O2,     0,       0x1400 },
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  { "ixw",      O2,     0,       0x1500 },
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  { "and",      O2,     0,       0x1600 },
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  { "xor",      O2,     0,       0x1700 },
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  { "mtcr",     OC,     0,       0x1800 },
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  { "asr",      O2,     0,       0x1A00 },
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  { "lsl",      O2,     0,       0x1B00 },
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  { "addu",     O2,     0,       0x1C00 },
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  { "add",      O2,     0,       0x1C00 }, /* Official alias.  */
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  { "ixh",      O2,     0,       0x1D00 },
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  { "or",       O2,     0,       0x1E00 },
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  { "andn",     O2,     0,       0x1F00 },
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  { "addi",     OI,     0,       0x2000 },
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#define MCORE_INST_ADDI 0x2000
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  { "cmplti",   OI,     0,       0x2200 },
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  { "subi",     OI,     0,       0x2400 },
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/* SPACE: 0x2600-0x27ff open for a register+immediate  operation */
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  { "rsubi",    OB,     0,       0x2800 },
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  { "cmpnei",   OB,     0,       0x2A00 },
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  { "bmaski",   OMa,    0,       0x2C00 },
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  { "divu",     O1R1,   0,       0x2C10 },
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/* SPACE:                       0x2c20 - 0x2c7f */
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  { "bmaski",   OMb,    0,       0x2C80 },
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  { "bmaski",   OMc,    0,       0x2D00 },
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  { "andi",     OB,     0,       0x2E00 },
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  { "bclri",    OB,     0,       0x3000 },
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/* SPACE:                       0x3200 - 0x320f */
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  { "divs",     O1R1,   0,       0x3210 },
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/* SPACE:                       0x3220 - 0x326f */
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  { "bgeni",    OBRa,   0,       0x3270 },
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  { "bgeni",    OBRb,   0,       0x3280 },
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  { "bgeni",    OBRc,   0,       0x3300 },
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  { "bseti",    OB,     0,       0x3400 },
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  { "btsti",    OB,     0,       0x3600 },
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  { "xsr",      O1,     0,       0x3800 },
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  { "rotli",    SIa,    0,       0x3800 },
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  { "asrc",     O1,     0,       0x3A00 },
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  { "asri",     SIa,    0,       0x3A00 },
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  { "lslc",     O1,     0,       0x3C00 },
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  { "lsli",     SIa,    0,       0x3C00 },
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  { "lsrc",     O1,     0,       0x3E00 },
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  { "lsri",     SIa,    0,       0x3E00 },
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/* SPACE:                       0x4000 - 0x5fff */
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  { "movi",     I7,     0,       0x6000 },
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#define MCORE_INST_BMASKI_ALT   0x6000
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#define MCORE_INST_BGENI_ALT    0x6000
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  { "mulsh",    MULSH,  0,      0x6800 },
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  { "muls.h",   MULSH,  0,      0x6800 },
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/* SPACE:                       0x6900 - 0x6FFF */
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  { "jmpi",     LJ,     1,      0x7000 },
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  { "jsri",     LJ,     0,       0x7F00 },
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#define MCORE_INST_JMPI 0x7000
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  { "lrw",      LR,     0,       0x7000 },
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#define MCORE_INST_JSRI 0x7F00
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  { "ld",       LS,     0,       0x8000 },
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  { "ldw",      LS,     0,       0x8000 },
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  { "ld.w",     LS,     0,       0x8000 },
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  { "st",       LS,     0,       0x9000 },
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  { "stw",      LS,     0,       0x9000 },
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  { "st.w",     LS,     0,       0x9000 },
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  { "ldb",      LS,     0,       0xA000 },
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  { "ld.b",     LS,     0,       0xA000 },
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  { "stb",      LS,     0,       0xB000 },
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  { "st.b",     LS,     0,       0xB000 },
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  { "ldh",      LS,     0,       0xC000 },
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  { "ld.h",     LS,     0,       0xC000 },
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  { "sth",      LS,     0,       0xD000 },
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  { "st.h",     LS,     0,       0xD000 },
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  { "bt",       BR,     0,       0xE000 },
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  { "bf",       BR,     0,       0xE800 },
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  { "br",       BR,     1,      0xF000 },
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#define MCORE_INST_BR   0xF000
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  { "bsr",      BR,     0,       0xF800 },
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#define MCORE_INST_BSR  0xF800
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/* The following are relaxable branches */
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  { "jbt",      JC,     0,       0xE000 },
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  { "jbf",      JC,     0,       0xE800 },
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  { "jbr",      JU,     1,      0xF000 },
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  { "jbsr",     JL,     0,       0xF800 },
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/* The following are aliases for other instructions */
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  { "rts",      O0,     2,      0x00CF },  /* jmp r15 */
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  { "rolc",     DO21,   0,       0x0600 },  /* addc rd,rd */
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  { "rotlc",    DO21,   0,       0x0600 },  /* addc rd,rd */
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  { "setc",     O0,     0,       0x0C00 },  /* cmphs r0,r0 */
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  { "clrc",     O0,     0,       0x0F00 },  /* cmpne r0,r0 */
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  { "tstle",    O1,     0,       0x2200 },  /* cmplti rd,1 */
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  { "cmplei",   OB,     0,       0x2200 },  /* cmplei rd,X -> cmplti rd,X+1 */
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  { "neg",      O1,     0,       0x2800 },  /* rsubi rd,0 */
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  { "tstne",    O1,     0,       0x2A00 },  /* cmpnei rd,0 */
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  { "tstlt",    O1,     0,       0x37F0 },  /* btsti rx,31 */
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  { "mclri",    OB2,    0,       0x3000 },  /* bclri rx,log2(imm) */
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  { "mgeni",    OBR2,   0,       0x3200 },  /* bgeni rx,log2(imm) */
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  { "mseti",    OB2,    0,       0x3400 },  /* bseti rx,log2(imm) */
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  { "mtsti",    OB2,    0,       0x3600 },  /* btsti rx,log2(imm) */
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  { "rori",     RSI,    0,       0x3800 },
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  { "rotri",    RSI,    0,       0x3800 },
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  { "nop",      O0,     0,       0x1200 },  /* mov r0, r0 */
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  { 0,           0,       0,      0 }
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};
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#endif

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