OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [common/] [sim-reason.c] - Blame information for rev 857

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Generic simulator stop_reason.
2
   Copyright (C) 1997, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
   Contributed by Cygnus Support.
4
 
5
This file is part of GDB, the GNU debugger.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3 of the License, or
10
(at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "sim-main.h"
21
#include "sim-assert.h"
22
 
23
/* Generic implementation of sim_stop_reason */
24
 
25
void
26
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
27
{
28
  sim_engine *engine = NULL;
29
  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
30
  engine = STATE_ENGINE (sd);
31
  *reason = engine->reason;
32
  switch (*reason)
33
    {
34
    case sim_exited :
35
      *sigrc = engine->sigrc;
36
      break;
37
    case sim_stopped :
38
    case sim_signalled :
39
      *sigrc = sim_signal_to_target (sd, engine->sigrc);
40
      break;
41
    default :
42
      abort ();
43
    }
44
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.