OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [cr16/] [ChangeLog] - Blame information for rev 824

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
2010-01-09  Ralf Wildenhues  
2
 
3
        * configure: Regenerate.
4
 
5
2009-08-22  Ralf Wildenhues  
6
 
7
        * config.in: Regenerate.
8
        * configure: Likewise.
9
 
10
        * configure: Regenerate.
11
 
12
2008-07-11  Hans-Peter Nilsson  
13
 
14
        * configure: Regenerate to track ../common/common.m4 changes.
15
        * config.in: Ditto.
16
 
17
        * interp.c (hash): Remove incorrect prototype.
18
 
19
2008-06-06  Vladimir Prus  
20
            Daniel Jacobowitz  
21
            Joseph Myers  
22
 
23
        * configure: Regenerate.
24
 
25
2008-05-02  M Ranga Swami Reddy 
26
 
27
        * interp.c: Update the machine code decode algorithm using hash table.
28
        * Makefile.in, cr16_sim.h, gencode.c and  simops.c: Update for typos
29
        and coding standards.
30
 
31
2008-02-12  M Ranga Swami Reddy 
32
 
33
        * ChangeLog, Makefile.in, configure, configure.in, cr16_sim.h,
34
        gencode.c, interp.c, simops.c, endian.c: Created.
35
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.