OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [frv/] [profile-fr450.c] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* frv simulator fr450 dependent profiling code.
2
 
3
   Copyright (C) 2001, 2004, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
   Contributed by Red Hat
6
 
7
This file is part of the GNU simulators.
8
 
9
This program is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3 of the License, or
12
(at your option) any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
 
22
*/
23
#define WANT_CPU
24
#define WANT_CPU_FRVBF
25
 
26
#include "sim-main.h"
27
#include "bfd.h"
28
 
29
#if WITH_PROFILE_MODEL_P
30
 
31
#include "profile.h"
32
#include "profile-fr400.h"
33
 
34
int
35
frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
36
                            int unit_num, int referenced)
37
{
38
  return idesc->timing->units[unit_num].done;
39
}
40
 
41
int
42
frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
43
                             int unit_num, int referenced,
44
                             INT in_GRi, INT in_GRj, INT out_GRk,
45
                             INT out_ICCi_1)
46
{
47
  /* Modelling for this unit is the same as for fr500.  */
48
  return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
49
                                      in_GRi, in_GRj, out_GRk, out_ICCi_1);
50
}
51
 
52
int
53
frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
54
                          int unit_num, int referenced,
55
                          INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
56
{
57
  int cycles;
58
 
59
  if (model_insn == FRV_INSN_MODEL_PASS_1)
60
    {
61
      /* Pass 1 is the same as for fr500.  */
62
      return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
63
                                       in_GRi, in_GRj, out_GRk, out_ICCi_1);
64
    }
65
 
66
  /* icc0-icc4 are the upper 4 fields of the CCR.  */
67
  if (out_ICCi_1 >= 0)
68
    out_ICCi_1 += 4;
69
 
70
  /* GRk and IACCi_1 have a latency of 1 cycle.  */
71
  cycles = idesc->timing->units[unit_num].done;
72
  update_GRdouble_latency (cpu, out_GRk, cycles + 1);
73
  update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
74
 
75
  return cycles;
76
}
77
 
78
int
79
frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
80
                          int unit_num, int referenced,
81
                          INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
82
{
83
  int cycles;
84
 
85
  if (model_insn == FRV_INSN_MODEL_PASS_1)
86
    {
87
      /* Pass 1 is the same as for fr500.  */
88
      return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
89
                                       in_GRi, in_GRj, out_GRk, out_ICCi_1);
90
    }
91
 
92
  /* icc0-icc4 are the upper 4 fields of the CCR.  */
93
  if (out_ICCi_1 >= 0)
94
    out_ICCi_1 += 4;
95
 
96
  /* GRk, ICCi_1 and the divider have a latency of 18 cycles  */
97
  cycles = idesc->timing->units[unit_num].done;
98
  update_GR_latency (cpu, out_GRk, cycles + 18);
99
  update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
100
  update_idiv_resource_latency (cpu, 0, cycles + 18);
101
 
102
  return cycles;
103
}
104
 
105
int
106
frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
107
                            int unit_num, int referenced,
108
                            INT in_GRi, INT in_GRj,
109
                            INT in_ICCi_2, INT in_ICCi_3)
110
{
111
  /* Modelling for this unit is the same as for fr400.  */
112
  return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
113
                                     in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
114
}
115
 
116
int
117
frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
118
                          int unit_num, int referenced,
119
                          INT in_GRi, INT in_GRj,
120
                          INT in_ICCi_2, INT in_FCCi_2)
121
{
122
  /* Modelling for this unit is the same as for fr500.  */
123
  return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
124
                                   in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
125
}
126
 
127
int
128
frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
129
                           int unit_num, int referenced,
130
                           INT in_ICCi_3, INT in_FCCi_3)
131
{
132
  /* Modelling for this unit is the same as for fr500.  */
133
  return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
134
                                    in_ICCi_3, in_FCCi_3);
135
}
136
 
137
int
138
frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
139
                             int unit_num, int referenced,
140
                             INT out_GRkhi, INT out_GRklo)
141
{
142
  /* Modelling for this unit is the same as for fr500.  */
143
  return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
144
                                       out_GRkhi, out_GRklo);
145
}
146
 
147
int
148
frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
149
                             int unit_num, int referenced,
150
                             INT in_GRi, INT in_GRj,
151
                             INT out_GRk, INT out_GRdoublek)
152
{
153
  int cycles;
154
 
155
  if (model_insn == FRV_INSN_MODEL_PASS_1)
156
    {
157
      /* Pass 1 is the same as for fr500.  */
158
      return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
159
                                          in_GRi, in_GRj, out_GRk,
160
                                          out_GRdoublek);
161
    }
162
 
163
  cycles = idesc->timing->units[unit_num].done;
164
 
165
  /* The latency of GRk for a load will depend on how long it takes to retrieve
166
     the the data from the cache or memory.  */
167
  update_GR_latency_for_load (cpu, out_GRk, cycles);
168
  update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
169
 
170
  if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
171
    {
172
      /* GNER has a latency of 2 cycles.  */
173
      update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
174
      update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
175
    }
176
 
177
  return cycles;
178
}
179
 
180
int
181
frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
182
                              int unit_num, int referenced,
183
                              INT in_GRi, INT in_GRj,
184
                              INT in_GRk, INT in_GRdoublek)
185
{
186
  /* Modelling for this unit is the same as for fr500.  */
187
  return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
188
                                       in_GRi, in_GRj, in_GRk, in_GRdoublek);
189
}
190
 
191
int
192
frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
193
                             int unit_num, int referenced,
194
                             INT in_GRi, INT in_GRj,
195
                             INT out_FRk, INT out_FRdoublek)
196
{
197
  /* Modelling for this unit is the same as for fr400.  */
198
  return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
199
                                      in_GRi, in_GRj, out_FRk, out_FRdoublek);
200
}
201
 
202
int
203
frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
204
                              int unit_num, int referenced,
205
                              INT in_GRi, INT in_GRj,
206
                              INT in_FRk, INT in_FRdoublek)
207
{
208
  /* Modelling for this unit is the same as for fr400.  */
209
  return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
210
                                      in_GRi, in_GRj, in_FRk, in_FRdoublek);
211
}
212
 
213
int
214
frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
215
                          int unit_num, int referenced,
216
                          INT in_GRi, INT in_GRj, INT out_GRk)
217
{
218
  /* Modelling for this unit is the same as for fr500.  */
219
  return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
220
                                   in_GRi, in_GRj, out_GRk);
221
}
222
 
223
int
224
frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
225
                           int unit_num, int referenced,
226
                           INT in_FRk, INT out_GRj)
227
{
228
  int cycles;
229
 
230
  if (model_insn == FRV_INSN_MODEL_PASS_1)
231
    {
232
      /* Pass 1 is the same as for fr400.  */
233
      return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
234
                                        in_FRk, out_GRj);
235
    }
236
 
237
  /* The latency of GRj is 1 cycle.  */
238
  cycles = idesc->timing->units[unit_num].done;
239
  update_GR_latency (cpu, out_GRj, cycles + 1);
240
 
241
  return cycles;
242
}
243
 
244
int
245
frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
246
                           int unit_num, int referenced,
247
                           INT in_spr, INT out_GRj)
248
{
249
  /* Modelling for this unit is the same as for fr500.  */
250
  return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
251
                                     in_spr, out_GRj);
252
}
253
 
254
int
255
frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
256
                           int unit_num, int referenced,
257
                           INT in_GRj, INT out_FRk)
258
{
259
  /* Modelling for this unit is the same as for fr400.  */
260
  return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
261
                                    in_GRj, out_FRk);
262
}
263
 
264
int
265
frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
266
                            int unit_num, int referenced,
267
                            INT in_GRj, INT out_spr)
268
{
269
  /* Modelling for this unit is the same as for fr500.  */
270
  return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
271
                                     in_GRj, out_spr);
272
}
273
 
274
int
275
frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
276
                             int unit_num, int referenced,
277
                             INT in_FRi, INT in_FRj,
278
                             INT out_FRk)
279
{
280
  /* Modelling for this unit is the same as for fr400.  */
281
  return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
282
                                      in_FRi, in_FRj, out_FRk);
283
}
284
 
285
int
286
frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
287
                                  int unit_num, int referenced,
288
                                  INT in_FRi, INT in_FRj,
289
                                  INT out_FRk)
290
{
291
  /* Modelling for this unit is the same as for fr400.  */
292
  return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
293
                                           in_FRi, in_FRj, out_FRk);
294
}
295
 
296
int
297
frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
298
                                int unit_num, int referenced,
299
                                INT out_FRkhi, INT out_FRklo)
300
{
301
  /* Modelling for this unit is the same as for fr400.  */
302
  return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
303
                                         out_FRkhi, out_FRklo);
304
}
305
 
306
int
307
frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
308
                             int unit_num, int referenced,
309
                             INT in_FRi, INT in_FRj,
310
                             INT out_ACC40Sk, INT out_ACC40Uk)
311
{
312
  /* Modelling for this unit is the same as for fr400.  */
313
  return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
314
                                      in_FRi, in_FRj, out_ACC40Sk,
315
                                      out_ACC40Uk);
316
}
317
 
318
int
319
frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
320
                                  int unit_num, int referenced,
321
                                  INT in_FRi, INT in_FRj,
322
                                  INT out_ACC40Sk, INT out_ACC40Uk)
323
{
324
  /* Modelling for this unit is the same as for fr400.  */
325
  return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
326
                                           in_FRi, in_FRj, out_ACC40Sk,
327
                                           out_ACC40Uk);
328
}
329
 
330
int
331
frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
332
                                 int unit_num, int referenced,
333
                                 INT in_ACC40Si, INT out_ACC40Sk)
334
{
335
  /* Modelling for this unit is the same as for fr400.  */
336
  return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
337
                                          in_ACC40Si, out_ACC40Sk);
338
}
339
 
340
int
341
frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
342
                                      int unit_num, int referenced,
343
                                      INT in_ACC40Si, INT out_ACC40Sk)
344
{
345
  /* Modelling for this unit is the same as for fr400.  */
346
  return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
347
                                               referenced, in_ACC40Si,
348
                                               out_ACC40Sk);
349
}
350
 
351
int
352
frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
353
                                     int unit_num, int referenced,
354
                                     INT in_ACC40Si, INT out_ACC40Sk)
355
{
356
  /* Modelling for this unit is the same as for fr400.  */
357
  return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
358
                                              referenced, in_ACC40Si,
359
                                              out_ACC40Sk);
360
}
361
 
362
int
363
frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
364
                                          int unit_num, int referenced,
365
                                          INT in_ACC40Si, INT out_ACC40Sk)
366
{
367
  /* Modelling for this unit is the same as for fr400.  */
368
  return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
369
                                                   referenced, in_ACC40Si,
370
                                                   out_ACC40Sk);
371
}
372
 
373
int
374
frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
375
                             int unit_num, int referenced,
376
                             INT in_FRi, INT in_FRj,
377
                             INT out_FRk)
378
{
379
  /* Modelling is the same as media unit 1.  */
380
  return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
381
                                      in_FRi, in_FRj, out_FRk);
382
}
383
 
384
int
385
frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
386
                                  int unit_num, int referenced,
387
                                  INT in_FRi, INT out_FRk)
388
{
389
  /* Modelling for this unit is the same as for fr400.  */
390
  return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
391
                                           in_FRi, out_FRk);
392
}
393
 
394
int
395
frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
396
                                  int unit_num, int referenced,
397
                                  INT in_FRi, INT in_FRj,
398
                                  INT out_FRk)
399
{
400
  /* Modelling is the same as media unit 1.  */
401
  return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
402
                                           in_FRi, in_FRj, out_FRk);
403
}
404
 
405
int
406
frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
407
                             int unit_num, int referenced,
408
                             INT in_ACC40Si, INT in_FRj,
409
                             INT out_ACC40Sk, INT out_FRk)
410
{
411
  /* Modelling for this unit is the same as for fr400.  */
412
  return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
413
                                      in_ACC40Si, in_FRj,
414
                                      out_ACC40Sk, out_FRk);
415
}
416
 
417
int
418
frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
419
                                  int unit_num, int referenced,
420
                                  INT in_ACCGi, INT in_FRinti,
421
                                  INT out_ACCGk, INT out_FRintk)
422
{
423
  /* Modelling is the same as media-4 unit except use accumulator guards
424
     as input instead of accumulators.  */
425
  return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
426
                                      in_ACCGi, in_FRinti,
427
                                      out_ACCGk, out_FRintk);
428
}
429
 
430
int
431
frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
432
                                      int unit_num, int referenced,
433
                                      INT in_ACC40Si, INT out_FRk)
434
{
435
  /* Modelling for this unit is the same as for fr400.  */
436
  return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
437
                                               referenced, in_ACC40Si,
438
                                               out_FRk);
439
}
440
 
441
int
442
frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
443
                                      int unit_num, int referenced)
444
{
445
  int cycles;
446
  int acc;
447
  FRV_PROFILE_STATE *ps;
448
 
449
  if (model_insn == FRV_INSN_MODEL_PASS_1)
450
    return 0;
451
 
452
  /* The preprocessing can execute right away.  */
453
  cycles = idesc->timing->units[unit_num].done;
454
 
455
  ps = CPU_PROFILE_STATE (cpu);
456
 
457
  /* The post processing must wait for any pending ACC writes.  */
458
  ps->post_wait = cycles;
459
  for (acc = 0; acc < 4; acc++)
460
    post_wait_for_ACC (cpu, acc);
461
  for (acc = 8; acc < 12; acc++)
462
    post_wait_for_ACC (cpu, acc);
463
 
464
  for (acc = 0; acc < 4; acc++)
465
    {
466
      update_ACC_latency (cpu, acc, ps->post_wait);
467
      update_ACC_ptime (cpu, acc, 2);
468
    }
469
  for (acc = 8; acc < 12; acc++)
470
    {
471
      update_ACC_latency (cpu, acc, ps->post_wait);
472
      update_ACC_ptime (cpu, acc, 2);
473
    }
474
 
475
  return cycles;
476
}
477
 
478
int
479
frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
480
                             int unit_num, int referenced,
481
                             INT in_FRi, INT out_FRk)
482
{
483
  /* Modelling for this unit is the same as for fr400.  */
484
  return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
485
                                      in_FRi, out_FRk);
486
}
487
 
488
int
489
frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
490
                             int unit_num, int referenced,
491
                             INT in_FRinti, INT in_FRintj,
492
                             INT out_FCCk)
493
{
494
  /* Modelling for this unit is the same as for fr400.  */
495
  return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
496
                                      in_FRinti, in_FRintj, out_FCCk);
497
}
498
 
499
int
500
frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
501
                                       int unit_num, int referenced,
502
                                       INT in_FRi,
503
                                       INT out_FRk)
504
{
505
  /* Modelling for this unit is the same as for fr400.  */
506
  return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
507
                                                referenced, in_FRi, out_FRk);
508
}
509
 
510
int
511
frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
512
                                     int unit_num, int referenced,
513
                                     INT in_FRj,
514
                                     INT out_FRk)
515
{
516
  /* Modelling for this unit is the same as for fr400.  */
517
  return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
518
                                              referenced, in_FRj, out_FRk);
519
}
520
 
521
int
522
frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
523
                         int unit_num, int referenced,
524
                         INT in_GRi, INT in_GRj)
525
{
526
  /* Modelling for this unit is the same as for fr500.  */
527
  return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
528
                                  in_GRi, in_GRj);
529
}
530
 
531
int
532
frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
533
                         int unit_num, int referenced,
534
                         INT in_GRi, INT in_GRj)
535
{
536
  /* Modelling for this unit is the same as for fr500.  */
537
  return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
538
                                  in_GRi, in_GRj);
539
}
540
 
541
int
542
frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
543
                         int unit_num, int referenced,
544
                         INT in_GRi, INT in_GRj)
545
{
546
  /* Modelling for this unit is the same as for fr500.  */
547
  return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
548
                                  in_GRi, in_GRj);
549
}
550
 
551
int
552
frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
553
                          int unit_num, int referenced,
554
                          INT in_GRi, INT in_GRj)
555
{
556
  /* Modelling for this unit is the same as for fr500.  */
557
  return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
558
                                   in_GRi, in_GRj);
559
}
560
 
561
int
562
frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
563
                          int unit_num, int referenced,
564
                          INT in_GRi, INT in_GRj)
565
{
566
  /* Modelling for this unit is the same as for fr500.  */
567
  return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
568
                                   in_GRi, in_GRj);
569
}
570
 
571
int
572
frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
573
                          int unit_num, int referenced,
574
                          INT in_GRi, INT in_GRj)
575
{
576
  /* Modelling for this unit is the same as for fr500.  */
577
  return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
578
                                   in_GRi, in_GRj);
579
}
580
 
581
int
582
frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
583
                          int unit_num, int referenced,
584
                          INT in_GRi, INT in_GRj)
585
{
586
  /* Modelling for this unit is the same as for fr500.  */
587
  return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
588
                                   in_GRi, in_GRj);
589
}
590
 
591
int
592
frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
593
                             int unit_num, int referenced)
594
{
595
  /* Modelling for this unit is the same as for fr500.  */
596
  return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
597
}
598
 
599
int
600
frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
601
                            int unit_num, int referenced)
602
{
603
  /* Modelling for this unit is the same as for fr500.  */
604
  return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
605
}
606
 
607
#endif /* WITH_PROFILE_MODEL_P */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.