| 1 |
227 |
jeremybenn |
/* Register definitions for the FRV simulator
|
| 2 |
|
|
Copyright (C) 2000, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
|
| 3 |
|
|
Contributed by Red Hat.
|
| 4 |
|
|
|
| 5 |
|
|
This file is part of the GNU Simulators.
|
| 6 |
|
|
|
| 7 |
|
|
This program is free software; you can redistribute it and/or modify
|
| 8 |
|
|
it under the terms of the GNU General Public License as published by
|
| 9 |
|
|
the Free Software Foundation; either version 3 of the License, or
|
| 10 |
|
|
(at your option) any later version.
|
| 11 |
|
|
|
| 12 |
|
|
This program is distributed in the hope that it will be useful,
|
| 13 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 14 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 15 |
|
|
GNU General Public License for more details.
|
| 16 |
|
|
|
| 17 |
|
|
You should have received a copy of the GNU General Public License
|
| 18 |
|
|
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
| 19 |
|
|
|
| 20 |
|
|
#ifndef REGISTERS_H
|
| 21 |
|
|
#define REGISTERS_H
|
| 22 |
|
|
|
| 23 |
|
|
#define FRV_MAX_GR 64
|
| 24 |
|
|
#define FRV_MAX_FR 64
|
| 25 |
|
|
#define FRV_MAX_CPR 64
|
| 26 |
|
|
#define FRV_MAX_SPR 4096
|
| 27 |
|
|
|
| 28 |
|
|
/* Register init, reset values and read_only masks. */
|
| 29 |
|
|
typedef struct
|
| 30 |
|
|
{
|
| 31 |
|
|
USI init_value; /* initial value */
|
| 32 |
|
|
USI reset_value; /* value for software reset */
|
| 33 |
|
|
USI reset_mask; /* bits which are reset */
|
| 34 |
|
|
USI read_only_mask; /* bits which are read-only */
|
| 35 |
|
|
char implemented; /* 1==register is implemented */
|
| 36 |
|
|
char supervisor; /* 1==register is supervisor-only */
|
| 37 |
|
|
} FRV_SPR_CONTROL_INFO;
|
| 38 |
|
|
|
| 39 |
|
|
typedef struct
|
| 40 |
|
|
{
|
| 41 |
|
|
int fr; /* FR registers implemented */
|
| 42 |
|
|
int cpr; /* coprocessor registers implemented */
|
| 43 |
|
|
FRV_SPR_CONTROL_INFO *spr; /* SPR implementation details */
|
| 44 |
|
|
} FRV_REGISTER_CONTROL;
|
| 45 |
|
|
|
| 46 |
|
|
void frv_register_control_init (SIM_CPU *);
|
| 47 |
|
|
void frv_initialize_spr (SIM_CPU *);
|
| 48 |
|
|
void frv_reset_spr (SIM_CPU *);
|
| 49 |
|
|
|
| 50 |
|
|
void frv_check_spr_access (SIM_CPU *, UINT);
|
| 51 |
|
|
|
| 52 |
|
|
void frv_fr_registers_available (SIM_CPU *, int *, int *);
|
| 53 |
|
|
void frv_gr_registers_available (SIM_CPU *, int *, int *);
|
| 54 |
|
|
int frv_check_register_access (SIM_CPU *, SI, int, int);
|
| 55 |
|
|
int frv_check_gr_access (SIM_CPU *, SI);
|
| 56 |
|
|
int frv_check_fr_access (SIM_CPU *, SI);
|
| 57 |
|
|
|
| 58 |
|
|
#endif /* REGISTERS_H */
|
