OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [h8300/] [sim-main.h] - Blame information for rev 853

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Main header for the Hitachi h8/300 architecture.  */
2
 
3
#include "bfd.h"
4
 
5
#ifndef SIM_MAIN_H
6
#define SIM_MAIN_H
7
 
8
#define DEBUG
9
 
10
/* These define the size of main memory for the simulator.
11
 
12
   Note the size of main memory for the H8/300H is only 256k.  Keeping it
13
   small makes the simulator run much faster and consume less memory.
14
 
15
   The linker knows about the limited size of the simulator's main memory
16
   on the H8/300H (via the h8300h.sc linker script).  So if you change
17
   H8300H_MSIZE, be sure to fix the linker script too.
18
 
19
   Also note that there's a separate "eightbit" area aside from main
20
   memory.  For simplicity, the simulator assumes any data memory reference
21
   outside of main memory refers to the eightbit area (in theory, this
22
   can only happen when simulating H8/300H programs).  We make no attempt
23
   to catch overlapping addresses, wrapped addresses, etc etc.  */
24
 
25
#define H8300_MSIZE (1 << 16)
26
 
27
/* avolkov:
28
   Next 2 macros are ugly for any workstation, but while they're work.
29
   Memory size MUST be configurable.  */
30
#define H8300H_MSIZE (1 << 24) 
31
#define H8300S_MSIZE (1 << 24) 
32
 
33
#define CSIZE 1024
34
 
35
enum h8_regnum {
36
  R0_REGNUM = 0,
37
  R1_REGNUM = 1,
38
  R2_REGNUM = 2,
39
  R3_REGNUM = 3,
40
  R4_REGNUM = 4,
41
  R5_REGNUM = 5,
42
  R6_REGNUM = 6,
43
  R7_REGNUM = 7,
44
 
45
  SP_REGNUM = R7_REGNUM,        /* Contains address of top of stack */
46
  FP_REGNUM = R6_REGNUM,        /* Contains address of executing
47
                                   stack frame */
48
  CCR_REGNUM = 8,               /* Contains processor status */
49
  PC_REGNUM  = 9,               /* Contains program counter */
50
  CYCLE_REGNUM = 10,
51
  EXR_REGNUM  = 11,
52
  INST_REGNUM = 12,
53
  TICK_REGNUM = 13,
54
  MACH_REGNUM = 14,
55
  MACL_REGNUM = 15,
56
  SBR_REGNUM =  16,
57
  VBR_REGNUM =  17,
58
 
59
  ZERO_REGNUM = 18
60
};
61
 
62
enum h8_typecodes {
63
  OP_NULL,
64
  OP_REG,               /* Register direct.  */
65
  OP_LOWREG,            /* Special reg syntax for "bra".  */
66
  OP_DISP,              /* Register indirect w/displacement.  */
67
  /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
68
  OP_PREDEC,            /* Register indirect w/pre-decrement.  */
69
  OP_POSTDEC,           /* Register indirect w/post-decrement.  */
70
  OP_PREINC,            /* Register indirect w/pre-increment.  */
71
  OP_POSTINC,           /* Register indirect w/post-increment.  */
72
  OP_PCREL,             /* PC Relative.  */
73
  OP_MEM,               /* Absolute memory address.  */
74
  OP_CCR,               /* Condition Code Register.  */
75
  OP_IMM,               /* Immediate value.  */
76
  /*OP_ABS*/            /* Un-used (duplicates op_mem?).  */
77
  OP_EXR,               /* EXtended control Register.  */
78
  OP_SBR,               /* Vector Base Register.  */
79
  OP_VBR,               /* Short-address Base Register.  */
80
  OP_MACH,              /* Multiply Accumulator - high.  */
81
  OP_MACL,              /* Multiply Accumulator - low.   */
82
  /* FIXME: memory indirect?  */
83
  OP_INDEXB,            /* Byte index mode */
84
  OP_INDEXW,            /* Word index mode */
85
  OP_INDEXL             /* Long index mode */
86
};
87
 
88
#include "sim-basics.h"
89
 
90
/* Define sim_cia.  */
91
typedef unsigned32 sim_cia;
92
 
93
#include "sim-base.h"
94
 
95
/* Structure used to describe addressing */
96
 
97
typedef struct
98
{
99
  int type;
100
  int reg;
101
  int literal;
102
} ea_type;
103
 
104
/* Struct for instruction decoder.  */
105
typedef struct
106
{
107
  ea_type src;
108
  ea_type dst;
109
  ea_type op3;
110
  int opcode;
111
  int next_pc;
112
  int oldpc;
113
  int cycles;
114
#ifdef DEBUG
115
  struct h8_opcode *op;
116
#endif
117
} decoded_inst;
118
 
119
struct _sim_cpu {
120
  unsigned int regs[20];        /* 8 GR's plus ZERO, SBR, and VBR.  */
121
  unsigned int pc;
122
 
123
  int macS;                     /* MAC Saturating mode */
124
  int macV;                     /* MAC Overflow */
125
  int macN;                     /* MAC Negative */
126
  int macZ;                     /* MAC Zero     */
127
 
128
  int delayed_branch;
129
  char **command_line;          /* Pointer to command line arguments.  */
130
 
131
  unsigned char *memory;
132
  unsigned char *eightbit;
133
  int mask;
134
 
135
  sim_cpu_base base;
136
};
137
 
138
/* The sim_state struct.  */
139
struct sim_state {
140
  struct _sim_cpu *cpu;
141
  unsigned int sim_cache_size;
142
  decoded_inst *sim_cache;
143
  unsigned short *cache_idx;
144
  unsigned long memory_size;
145
  int cache_top;
146
  int compiles;
147
#ifdef ADEBUG
148
  int stats[O_LAST];
149
#endif
150
  sim_state_base base;
151
};
152
 
153
/* The current state of the processor; registers, memory, etc.  */
154
 
155
#define CIA_GET(CPU)            (cpu_get_pc (CPU))
156
#define CIA_SET(CPU, VAL)       (cpu_set_pc ((CPU), (VAL)))
157
#define STATE_CPU(SD, N)        ((SD)->cpu)     /* Single Processor.  */
158
#define cpu_set_pc(CPU, VAL)    (((CPU)->pc)  = (VAL))
159
#define cpu_get_pc(CPU)         (((CPU)->pc))
160
 
161
/* Magic numbers used to distinguish an exit from a breakpoint.  */
162
#define LIBC_EXIT_MAGIC1 0xdead 
163
#define LIBC_EXIT_MAGIC2 0xbeef 
164
/* Local version of macros for decoding exit status.
165
   (included here rather than try to find target version of wait.h)
166
*/
167
#define SIM_WIFEXITED(V)        (((V) & 0xff) == 0)
168
#define SIM_WIFSTOPPED(V)       (!SIM_WIFEXITED (V))
169
#define SIM_WEXITSTATUS(V)      (((V) >> 8) & 0xff)
170
#define SIM_WSTOPSIG(V)         ((V) & 0x7f)
171
 
172
#endif /* SIM_MAIN_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.