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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [lm32/] [dv-lm32timer.c] - Blame information for rev 856

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Line No. Rev Author Line
1 227 jeremybenn
/*  Lattice Mico32 timer model.
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    Contributed by Jon Beniston <jon@beniston.com>
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   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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   This file is part of GDB.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#include "sim-main.h"
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#include "hw-main.h"
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#include "sim-assert.h"
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struct lm32timer
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{
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  unsigned base;                /* Base address of this timer.  */
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  unsigned limit;               /* Limit address of this timer.  */
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  unsigned int status;
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  unsigned int control;
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  unsigned int period;
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  unsigned int snapshot;
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  struct hw_event *event;
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};
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/* Timer registers.  */
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#define LM32_TIMER_STATUS       0x0
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#define LM32_TIMER_CONTROL      0x4
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#define LM32_TIMER_PERIOD       0x8
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#define LM32_TIMER_SNAPSHOT     0xc
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/* Timer ports.  */
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enum
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{
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  INT_PORT
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};
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static const struct hw_port_descriptor lm32timer_ports[] = {
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  {"int", INT_PORT, 0, output_port},
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  {}
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};
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static void
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do_timer_event (struct hw *me, void *data)
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{
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  struct lm32timer *timer = hw_data (me);
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  /* Is timer started? */
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  if (timer->control & 0x4)
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    {
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      if (timer->snapshot)
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        {
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          /* Decrement timer.  */
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          timer->snapshot--;
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        }
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      else if (timer->control & 1)
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        {
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          /* Restart timer.  */
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          timer->snapshot = timer->period;
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        }
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    }
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  /* Generate interrupt when timer is at 0, and interrupt enable is 1.  */
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  if ((timer->snapshot == 0) && (timer->control & 1))
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    {
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      /* Generate interrupt.  */
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      hw_port_event (me, INT_PORT, 1);
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    }
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  /* If timer is started, schedule another event to decrement the timer again.  */
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  if (timer->control & 4)
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    hw_event_queue_schedule (me, 1, do_timer_event, 0);
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}
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static unsigned
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lm32timer_io_write_buffer (struct hw *me,
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                           const void *source,
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                           int space, unsigned_word base, unsigned nr_bytes)
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{
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  struct lm32timer *timers = hw_data (me);
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  int timer_reg;
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  const unsigned char *source_bytes = source;
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  int value = 0;
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  HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
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             (int) nr_bytes, value));
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  if (nr_bytes == 4)
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    value = (source_bytes[0] << 24)
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      | (source_bytes[1] << 16) | (source_bytes[2] << 8) | (source_bytes[3]);
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  else
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    hw_abort (me, "write with invalid number of bytes: %d", nr_bytes);
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  timer_reg = base - timers->base;
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  switch (timer_reg)
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    {
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    case LM32_TIMER_STATUS:
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      timers->status = value;
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      break;
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    case LM32_TIMER_CONTROL:
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      timers->control = value;
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      if (timers->control & 0x4)
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        {
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          /* Timer is started.  */
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          hw_event_queue_schedule (me, 1, do_timer_event, 0);
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        }
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      break;
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    case LM32_TIMER_PERIOD:
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      timers->period = value;
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      break;
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    default:
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      hw_abort (me, "invalid register address: 0x%x.", timer_reg);
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    }
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  return nr_bytes;
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}
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static unsigned
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lm32timer_io_read_buffer (struct hw *me,
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                          void *dest,
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                          int space, unsigned_word base, unsigned nr_bytes)
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{
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  struct lm32timer *timers = hw_data (me);
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  int timer_reg;
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  int value;
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  unsigned char *dest_bytes = dest;
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  HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));
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  timer_reg = base - timers->base;
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  switch (timer_reg)
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    {
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    case LM32_TIMER_STATUS:
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      value = timers->status;
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      break;
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    case LM32_TIMER_CONTROL:
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      value = timers->control;
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      break;
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    case LM32_TIMER_PERIOD:
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      value = timers->period;
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      break;
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    case LM32_TIMER_SNAPSHOT:
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      value = timers->snapshot;
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      break;
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    default:
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      hw_abort (me, "invalid register address: 0x%x.", timer_reg);
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    }
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  if (nr_bytes == 4)
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    {
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      dest_bytes[0] = value >> 24;
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      dest_bytes[1] = value >> 16;
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      dest_bytes[2] = value >> 8;
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      dest_bytes[3] = value;
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    }
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  else
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    hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);
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  return nr_bytes;
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}
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static void
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attach_lm32timer_regs (struct hw *me, struct lm32timer *timers)
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{
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  unsigned_word attach_address;
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  int attach_space;
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  unsigned attach_size;
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  reg_property_spec reg;
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  if (hw_find_property (me, "reg") == NULL)
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    hw_abort (me, "Missing \"reg\" property");
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  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
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    hw_abort (me, "\"reg\" property must contain three addr/size entries");
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  hw_unit_address_to_attach_address (hw_parent (me),
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                                     &reg.address,
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                                     &attach_space, &attach_address, me);
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  timers->base = attach_address;
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  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
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  timers->limit = attach_address + (attach_size - 1);
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  hw_attach_address (hw_parent (me),
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                     0, attach_space, attach_address, attach_size, me);
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}
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static void
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lm32timer_finish (struct hw *me)
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{
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  struct lm32timer *timers;
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  int i;
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  timers = HW_ZALLOC (me, struct lm32timer);
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  set_hw_data (me, timers);
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  set_hw_io_read_buffer (me, lm32timer_io_read_buffer);
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  set_hw_io_write_buffer (me, lm32timer_io_write_buffer);
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  set_hw_ports (me, lm32timer_ports);
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  /* Attach ourself to our parent bus.  */
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  attach_lm32timer_regs (me, timers);
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  /* Initialize the timers.  */
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  timers->status = 0;
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  timers->control = 0;
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  timers->period = 0;
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  timers->snapshot = 0;
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}
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const struct hw_descriptor dv_lm32timer_descriptor[] = {
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  {"lm32timer", lm32timer_finish,},
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  {NULL},
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};

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