OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [m32c/] [sample.S] - Blame information for rev 857

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
;;; sample.S --- simple test program for M32C simulator
2
;;;
3
;;; Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4
;;; Contributed by Red Hat, Inc.
5
;;;
6
;;; This file is part of the GNU simulators.
7
;;;
8
;;; This program is free software; you can redistribute it and/or modify
9
;;; it under the terms of the GNU General Public License as published by
10
;;; the Free Software Foundation; either version 3 of the License, or
11
;;; (at your option) any later version.
12
;;;
13
;;; This program is distributed in the hope that it will be useful,
14
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
;;; GNU General Public License for more details.
17
;;;
18
;;; You should have received a copy of the GNU General Public License
19
;;; along with this program.  If not, see .
20
 
21
;;; See the 'sample.x' and sample.mot targets in Makefile.in.
22
 
23
        .text
24
 
25
        .global _start
26
_start:
27
        mov.w   #0x1234,r1
28
        mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3
29
        brk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.