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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [m32r/] [cpux.h] - Blame information for rev 853

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Line No. Rev Author Line
1 227 jeremybenn 
/* CPU family header for m32rxf.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2010 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU simulators.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#ifndef CPU_M32RXF_H
26 
#define CPU_M32RXF_H
27 
 
28 
/* Maximum number of instructions that are fetched at a time.
29 
   This is for LIW type instructions sets (e.g. m32r).  */
30 
#define MAX_LIW_INSNS 2
31 
 
32 
/* Maximum number of instructions that can be executed in parallel.  */
33 
#define MAX_PARALLEL_INSNS 2
34 
 
35 
/* The size of an "int" needed to hold an instruction word.
36 
   This is usually 32 bits, but some architectures needs 64 bits.  */
37 
typedef CGEN_INSN_INT CGEN_INSN_WORD;
38 
 
39 
#include "cgen-engine.h"
40 
 
41 
/* CPU state information.  */
42 
typedef struct {
43 
  /* Hardware elements.  */
44 
  struct {
45 
  /* program counter */
46 
  USI h_pc;
47 
#define GET_H_PC() CPU (h_pc)
48 
#define SET_H_PC(x) (CPU (h_pc) = (x))
49 
  /* general registers */
50 
  SI h_gr[16];
51 
#define GET_H_GR(a1) CPU (h_gr)[a1]
52 
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
53 
  /* control registers */
54 
  USI h_cr[16];
55 
#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
56 
#define SET_H_CR(index, x) \
57 
do { \
58 
m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
59 
;} while (0)
60 
  /* accumulator */
61 
  DI h_accum;
62 
#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
63 
#define SET_H_ACCUM(x) \
64 
do { \
65 
m32rxf_h_accum_set_handler (current_cpu, (x));\
66 
;} while (0)
67 
  /* accumulators */
68 
  DI h_accums[2];
69 
#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
70 
#define SET_H_ACCUMS(index, x) \
71 
do { \
72 
m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
73 
;} while (0)
74 
  /* condition bit */
75 
  BI h_cond;
76 
#define GET_H_COND() CPU (h_cond)
77 
#define SET_H_COND(x) (CPU (h_cond) = (x))
78 
  /* psw part of psw */
79 
  UQI h_psw;
80 
#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
81 
#define SET_H_PSW(x) \
82 
do { \
83 
m32rxf_h_psw_set_handler (current_cpu, (x));\
84 
;} while (0)
85 
  /* backup psw */
86 
  UQI h_bpsw;
87 
#define GET_H_BPSW() CPU (h_bpsw)
88 
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
89 
  /* backup bpsw */
90 
  UQI h_bbpsw;
91 
#define GET_H_BBPSW() CPU (h_bbpsw)
92 
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
93 
  /* lock */
94 
  BI h_lock;
95 
#define GET_H_LOCK() CPU (h_lock)
96 
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
97 
  } hardware;
98 
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
99 
} M32RXF_CPU_DATA;
100 
 
101 
/* Cover fns for register access.  */
102 
USI m32rxf_h_pc_get (SIM_CPU *);
103 
void m32rxf_h_pc_set (SIM_CPU *, USI);
104 
SI m32rxf_h_gr_get (SIM_CPU *, UINT);
105 
void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
106 
USI m32rxf_h_cr_get (SIM_CPU *, UINT);
107 
void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
108 
DI m32rxf_h_accum_get (SIM_CPU *);
109 
void m32rxf_h_accum_set (SIM_CPU *, DI);
110 
DI m32rxf_h_accums_get (SIM_CPU *, UINT);
111 
void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
112 
BI m32rxf_h_cond_get (SIM_CPU *);
113 
void m32rxf_h_cond_set (SIM_CPU *, BI);
114 
UQI m32rxf_h_psw_get (SIM_CPU *);
115 
void m32rxf_h_psw_set (SIM_CPU *, UQI);
116 
UQI m32rxf_h_bpsw_get (SIM_CPU *);
117 
void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
118 
UQI m32rxf_h_bbpsw_get (SIM_CPU *);
119 
void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
120 
BI m32rxf_h_lock_get (SIM_CPU *);
121 
void m32rxf_h_lock_set (SIM_CPU *, BI);
122 
 
123 
/* These must be hand-written.  */
124 
extern CPUREG_FETCH_FN m32rxf_fetch_register;
125 
extern CPUREG_STORE_FN m32rxf_store_register;
126 
 
127 
typedef struct {
128 
  int empty;
129 
} MODEL_M32RX_DATA;
130 
 
131 
/* Instruction argument buffer.  */
132 
 
133 
union sem_fields {
134 
  struct { /* no operands */
135 
    int empty;
136 
  } sfmt_empty;
137 
  struct { /*  */
138 
    UINT f_uimm8;
139 
  } sfmt_clrpsw;
140 
  struct { /*  */
141 
    UINT f_uimm4;
142 
  } sfmt_trap;
143 
  struct { /*  */
144 
    IADDR i_disp24;
145 
    unsigned char out_h_gr_SI_14;
146 
  } sfmt_bl24;
147 
  struct { /*  */
148 
    IADDR i_disp8;
149 
    unsigned char out_h_gr_SI_14;
150 
  } sfmt_bl8;
151 
  struct { /*  */
152 
    SI f_imm1;
153 
    UINT f_accd;
154 
    UINT f_accs;
155 
  } sfmt_rac_dsi;
156 
  struct { /*  */
157 
    SI* i_dr;
158 
    UINT f_hi16;
159 
    UINT f_r1;
160 
    unsigned char out_dr;
161 
  } sfmt_seth;
162 
  struct { /*  */
163 
    SI* i_src1;
164 
    UINT f_accs;
165 
    UINT f_r1;
166 
    unsigned char in_src1;
167 
  } sfmt_mvtachi_a;
168 
  struct { /*  */
169 
    SI* i_dr;
170 
    UINT f_accs;
171 
    UINT f_r1;
172 
    unsigned char out_dr;
173 
  } sfmt_mvfachi_a;
174 
  struct { /*  */
175 
    ADDR i_uimm24;
176 
    SI* i_dr;
177 
    UINT f_r1;
178 
    unsigned char out_dr;
179 
  } sfmt_ld24;
180 
  struct { /*  */
181 
    SI* i_sr;
182 
    UINT f_r2;
183 
    unsigned char in_sr;
184 
    unsigned char out_h_gr_SI_14;
185 
  } sfmt_jl;
186 
  struct { /*  */
187 
    SI* i_sr;
188 
    INT f_simm16;
189 
    UINT f_r2;
190 
    UINT f_uimm3;
191 
    unsigned char in_sr;
192 
  } sfmt_bset;
193 
  struct { /*  */
194 
    SI* i_dr;
195 
    UINT f_r1;
196 
    UINT f_uimm5;
197 
    unsigned char in_dr;
198 
    unsigned char out_dr;
199 
  } sfmt_slli;
200 
  struct { /*  */
201 
    SI* i_dr;
202 
    INT f_simm8;
203 
    UINT f_r1;
204 
    unsigned char in_dr;
205 
    unsigned char out_dr;
206 
  } sfmt_addi;
207 
  struct { /*  */
208 
    SI* i_src1;
209 
    SI* i_src2;
210 
    UINT f_r1;
211 
    UINT f_r2;
212 
    unsigned char in_src1;
213 
    unsigned char in_src2;
214 
    unsigned char out_src2;
215 
  } sfmt_st_plus;
216 
  struct { /*  */
217 
    SI* i_src1;
218 
    SI* i_src2;
219 
    INT f_simm16;
220 
    UINT f_r1;
221 
    UINT f_r2;
222 
    unsigned char in_src1;
223 
    unsigned char in_src2;
224 
  } sfmt_st_d;
225 
  struct { /*  */
226 
    SI* i_src1;
227 
    SI* i_src2;
228 
    UINT f_acc;
229 
    UINT f_r1;
230 
    UINT f_r2;
231 
    unsigned char in_src1;
232 
    unsigned char in_src2;
233 
  } sfmt_machi_a;
234 
  struct { /*  */
235 
    SI* i_dr;
236 
    SI* i_sr;
237 
    UINT f_r1;
238 
    UINT f_r2;
239 
    unsigned char in_sr;
240 
    unsigned char out_dr;
241 
    unsigned char out_sr;
242 
  } sfmt_ld_plus;
243 
  struct { /*  */
244 
    IADDR i_disp16;
245 
    SI* i_src1;
246 
    SI* i_src2;
247 
    UINT f_r1;
248 
    UINT f_r2;
249 
    unsigned char in_src1;
250 
    unsigned char in_src2;
251 
  } sfmt_beq;
252 
  struct { /*  */
253 
    SI* i_dr;
254 
    SI* i_sr;
255 
    UINT f_r1;
256 
    UINT f_r2;
257 
    UINT f_uimm16;
258 
    unsigned char in_sr;
259 
    unsigned char out_dr;
260 
  } sfmt_and3;
261 
  struct { /*  */
262 
    SI* i_dr;
263 
    SI* i_sr;
264 
    INT f_simm16;
265 
    UINT f_r1;
266 
    UINT f_r2;
267 
    unsigned char in_sr;
268 
    unsigned char out_dr;
269 
  } sfmt_add3;
270 
  struct { /*  */
271 
    SI* i_dr;
272 
    SI* i_sr;
273 
    UINT f_r1;
274 
    UINT f_r2;
275 
    unsigned char in_dr;
276 
    unsigned char in_sr;
277 
    unsigned char out_dr;
278 
  } sfmt_add;
279 
#if WITH_SCACHE_PBB
280 
  /* Writeback handler.  */
281 
  struct {
282 
    /* Pointer to argbuf entry for insn whose results need writing back.  */
283 
    const struct argbuf *abuf;
284 
  } write;
285 
  /* x-before handler */
286 
  struct {
287 
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
288 
    int first_p;
289 
  } before;
290 
  /* x-after handler */
291 
  struct {
292 
    int empty;
293 
  } after;
294 
  /* This entry is used to terminate each pbb.  */
295 
  struct {
296 
    /* Number of insns in pbb.  */
297 
    int insn_count;
298 
    /* Next pbb to execute.  */
299 
    SCACHE *next;
300 
    SCACHE *branch_target;
301 
  } chain;
302 
#endif
303 
};
304 
 
305 
/* The ARGBUF struct.  */
306 
struct argbuf {
307 
  /* These are the baseclass definitions.  */
308 
  IADDR addr;
309 
  const IDESC *idesc;
310 
  char trace_p;
311 
  char profile_p;
312 
  /* ??? Temporary hack for skip insns.  */
313 
  char skip_count;
314 
  char unused;
315 
  /* cpu specific data follows */
316 
  union sem semantic;
317 
  int written;
318 
  union sem_fields fields;
319 
};
320 
 
321 
/* A cached insn.
322 
 
323 
   ??? SCACHE used to contain more than just argbuf.  We could delete the
324 
   type entirely and always just use ARGBUF, but for future concerns and as
325 
   a level of abstraction it is left in.  */
326 
 
327 
struct scache {
328 
  struct argbuf argbuf;
329 
};
330 
 
331 
/* Macros to simplify extraction, reading and semantic code.
332 
   These define and assign the local vars that contain the insn's fields.  */
333 
 
334 
#define EXTRACT_IFMT_EMPTY_VARS \
335 
  unsigned int length;
336 
#define EXTRACT_IFMT_EMPTY_CODE \
337 
  length = 0; \
338 
 
339 
#define EXTRACT_IFMT_ADD_VARS \
340 
  UINT f_op1; \
341 
  UINT f_r1; \
342 
  UINT f_op2; \
343 
  UINT f_r2; \
344 
  unsigned int length;
345 
#define EXTRACT_IFMT_ADD_CODE \
346 
  length = 2; \
347 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
348 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
349 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
350 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
351 
 
352 
#define EXTRACT_IFMT_ADD3_VARS \
353 
  UINT f_op1; \
354 
  UINT f_r1; \
355 
  UINT f_op2; \
356 
  UINT f_r2; \
357 
  INT f_simm16; \
358 
  unsigned int length;
359 
#define EXTRACT_IFMT_ADD3_CODE \
360 
  length = 4; \
361 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
362 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
363 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
364 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
365 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
366 
 
367 
#define EXTRACT_IFMT_AND3_VARS \
368 
  UINT f_op1; \
369 
  UINT f_r1; \
370 
  UINT f_op2; \
371 
  UINT f_r2; \
372 
  UINT f_uimm16; \
373 
  unsigned int length;
374 
#define EXTRACT_IFMT_AND3_CODE \
375 
  length = 4; \
376 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
377 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
378 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
379 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
380 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
381 
 
382 
#define EXTRACT_IFMT_OR3_VARS \
383 
  UINT f_op1; \
384 
  UINT f_r1; \
385 
  UINT f_op2; \
386 
  UINT f_r2; \
387 
  UINT f_uimm16; \
388 
  unsigned int length;
389 
#define EXTRACT_IFMT_OR3_CODE \
390 
  length = 4; \
391 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
392 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
393 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
394 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
395 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
396 
 
397 
#define EXTRACT_IFMT_ADDI_VARS \
398 
  UINT f_op1; \
399 
  UINT f_r1; \
400 
  INT f_simm8; \
401 
  unsigned int length;
402 
#define EXTRACT_IFMT_ADDI_CODE \
403 
  length = 2; \
404 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
405 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
406 
  f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
407 
 
408 
#define EXTRACT_IFMT_ADDV3_VARS \
409 
  UINT f_op1; \
410 
  UINT f_r1; \
411 
  UINT f_op2; \
412 
  UINT f_r2; \
413 
  INT f_simm16; \
414 
  unsigned int length;
415 
#define EXTRACT_IFMT_ADDV3_CODE \
416 
  length = 4; \
417 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
418 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
419 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
420 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
421 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
422 
 
423 
#define EXTRACT_IFMT_BC8_VARS \
424 
  UINT f_op1; \
425 
  UINT f_r1; \
426 
  SI f_disp8; \
427 
  unsigned int length;
428 
#define EXTRACT_IFMT_BC8_CODE \
429 
  length = 2; \
430 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
431 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
432 
  f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
433 
 
434 
#define EXTRACT_IFMT_BC24_VARS \
435 
  UINT f_op1; \
436 
  UINT f_r1; \
437 
  SI f_disp24; \
438 
  unsigned int length;
439 
#define EXTRACT_IFMT_BC24_CODE \
440 
  length = 4; \
441 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
442 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
443 
  f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
444 
 
445 
#define EXTRACT_IFMT_BEQ_VARS \
446 
  UINT f_op1; \
447 
  UINT f_r1; \
448 
  UINT f_op2; \
449 
  UINT f_r2; \
450 
  SI f_disp16; \
451 
  unsigned int length;
452 
#define EXTRACT_IFMT_BEQ_CODE \
453 
  length = 4; \
454 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
455 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
456 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
457 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
458 
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
459 
 
460 
#define EXTRACT_IFMT_BEQZ_VARS \
461 
  UINT f_op1; \
462 
  UINT f_r1; \
463 
  UINT f_op2; \
464 
  UINT f_r2; \
465 
  SI f_disp16; \
466 
  unsigned int length;
467 
#define EXTRACT_IFMT_BEQZ_CODE \
468 
  length = 4; \
469 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
470 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
471 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
472 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
473 
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
474 
 
475 
#define EXTRACT_IFMT_CMP_VARS \
476 
  UINT f_op1; \
477 
  UINT f_r1; \
478 
  UINT f_op2; \
479 
  UINT f_r2; \
480 
  unsigned int length;
481 
#define EXTRACT_IFMT_CMP_CODE \
482 
  length = 2; \
483 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
484 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
485 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
486 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
487 
 
488 
#define EXTRACT_IFMT_CMPI_VARS \
489 
  UINT f_op1; \
490 
  UINT f_r1; \
491 
  UINT f_op2; \
492 
  UINT f_r2; \
493 
  INT f_simm16; \
494 
  unsigned int length;
495 
#define EXTRACT_IFMT_CMPI_CODE \
496 
  length = 4; \
497 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
498 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
499 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
500 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
501 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
502 
 
503 
#define EXTRACT_IFMT_CMPZ_VARS \
504 
  UINT f_op1; \
505 
  UINT f_r1; \
506 
  UINT f_op2; \
507 
  UINT f_r2; \
508 
  unsigned int length;
509 
#define EXTRACT_IFMT_CMPZ_CODE \
510 
  length = 2; \
511 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
512 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
513 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
514 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
515 
 
516 
#define EXTRACT_IFMT_DIV_VARS \
517 
  UINT f_op1; \
518 
  UINT f_r1; \
519 
  UINT f_op2; \
520 
  UINT f_r2; \
521 
  INT f_simm16; \
522 
  unsigned int length;
523 
#define EXTRACT_IFMT_DIV_CODE \
524 
  length = 4; \
525 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
526 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
527 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
528 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
529 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
530 
 
531 
#define EXTRACT_IFMT_JC_VARS \
532 
  UINT f_op1; \
533 
  UINT f_r1; \
534 
  UINT f_op2; \
535 
  UINT f_r2; \
536 
  unsigned int length;
537 
#define EXTRACT_IFMT_JC_CODE \
538 
  length = 2; \
539 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
540 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
541 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
542 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
543 
 
544 
#define EXTRACT_IFMT_LD24_VARS \
545 
  UINT f_op1; \
546 
  UINT f_r1; \
547 
  UINT f_uimm24; \
548 
  unsigned int length;
549 
#define EXTRACT_IFMT_LD24_CODE \
550 
  length = 4; \
551 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
552 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
553 
  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
554 
 
555 
#define EXTRACT_IFMT_LDI16_VARS \
556 
  UINT f_op1; \
557 
  UINT f_r1; \
558 
  UINT f_op2; \
559 
  UINT f_r2; \
560 
  INT f_simm16; \
561 
  unsigned int length;
562 
#define EXTRACT_IFMT_LDI16_CODE \
563 
  length = 4; \
564 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
565 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
566 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
567 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
568 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
569 
 
570 
#define EXTRACT_IFMT_MACHI_A_VARS \
571 
  UINT f_op1; \
572 
  UINT f_r1; \
573 
  UINT f_acc; \
574 
  UINT f_op23; \
575 
  UINT f_r2; \
576 
  unsigned int length;
577 
#define EXTRACT_IFMT_MACHI_A_CODE \
578 
  length = 2; \
579 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 
  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
582 
  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
583 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
584 
 
585 
#define EXTRACT_IFMT_MVFACHI_A_VARS \
586 
  UINT f_op1; \
587 
  UINT f_r1; \
588 
  UINT f_op2; \
589 
  UINT f_accs; \
590 
  UINT f_op3; \
591 
  unsigned int length;
592 
#define EXTRACT_IFMT_MVFACHI_A_CODE \
593 
  length = 2; \
594 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
595 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
596 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
597 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
598 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
599 
 
600 
#define EXTRACT_IFMT_MVFC_VARS \
601 
  UINT f_op1; \
602 
  UINT f_r1; \
603 
  UINT f_op2; \
604 
  UINT f_r2; \
605 
  unsigned int length;
606 
#define EXTRACT_IFMT_MVFC_CODE \
607 
  length = 2; \
608 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
609 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
610 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
611 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
612 
 
613 
#define EXTRACT_IFMT_MVTACHI_A_VARS \
614 
  UINT f_op1; \
615 
  UINT f_r1; \
616 
  UINT f_op2; \
617 
  UINT f_accs; \
618 
  UINT f_op3; \
619 
  unsigned int length;
620 
#define EXTRACT_IFMT_MVTACHI_A_CODE \
621 
  length = 2; \
622 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
623 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
624 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
625 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
626 
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
627 
 
628 
#define EXTRACT_IFMT_MVTC_VARS \
629 
  UINT f_op1; \
630 
  UINT f_r1; \
631 
  UINT f_op2; \
632 
  UINT f_r2; \
633 
  unsigned int length;
634 
#define EXTRACT_IFMT_MVTC_CODE \
635 
  length = 2; \
636 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
637 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
638 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
639 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
640 
 
641 
#define EXTRACT_IFMT_NOP_VARS \
642 
  UINT f_op1; \
643 
  UINT f_r1; \
644 
  UINT f_op2; \
645 
  UINT f_r2; \
646 
  unsigned int length;
647 
#define EXTRACT_IFMT_NOP_CODE \
648 
  length = 2; \
649 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
650 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
651 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
652 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
653 
 
654 
#define EXTRACT_IFMT_RAC_DSI_VARS \
655 
  UINT f_op1; \
656 
  UINT f_accd; \
657 
  UINT f_bits67; \
658 
  UINT f_op2; \
659 
  UINT f_accs; \
660 
  UINT f_bit14; \
661 
  SI f_imm1; \
662 
  unsigned int length;
663 
#define EXTRACT_IFMT_RAC_DSI_CODE \
664 
  length = 2; \
665 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
666 
  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
667 
  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
668 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
669 
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
670 
  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
671 
  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
672 
 
673 
#define EXTRACT_IFMT_SETH_VARS \
674 
  UINT f_op1; \
675 
  UINT f_r1; \
676 
  UINT f_op2; \
677 
  UINT f_r2; \
678 
  UINT f_hi16; \
679 
  unsigned int length;
680 
#define EXTRACT_IFMT_SETH_CODE \
681 
  length = 4; \
682 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
683 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
684 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
685 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
686 
  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
687 
 
688 
#define EXTRACT_IFMT_SLLI_VARS \
689 
  UINT f_op1; \
690 
  UINT f_r1; \
691 
  UINT f_shift_op2; \
692 
  UINT f_uimm5; \
693 
  unsigned int length;
694 
#define EXTRACT_IFMT_SLLI_CODE \
695 
  length = 2; \
696 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
697 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
698 
  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
699 
  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
700 
 
701 
#define EXTRACT_IFMT_ST_D_VARS \
702 
  UINT f_op1; \
703 
  UINT f_r1; \
704 
  UINT f_op2; \
705 
  UINT f_r2; \
706 
  INT f_simm16; \
707 
  unsigned int length;
708 
#define EXTRACT_IFMT_ST_D_CODE \
709 
  length = 4; \
710 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
711 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
712 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
713 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
714 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
715 
 
716 
#define EXTRACT_IFMT_TRAP_VARS \
717 
  UINT f_op1; \
718 
  UINT f_r1; \
719 
  UINT f_op2; \
720 
  UINT f_uimm4; \
721 
  unsigned int length;
722 
#define EXTRACT_IFMT_TRAP_CODE \
723 
  length = 2; \
724 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
725 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
726 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
727 
  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
728 
 
729 
#define EXTRACT_IFMT_SATB_VARS \
730 
  UINT f_op1; \
731 
  UINT f_r1; \
732 
  UINT f_op2; \
733 
  UINT f_r2; \
734 
  UINT f_uimm16; \
735 
  unsigned int length;
736 
#define EXTRACT_IFMT_SATB_CODE \
737 
  length = 4; \
738 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
739 
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
740 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
741 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
742 
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
743 
 
744 
#define EXTRACT_IFMT_CLRPSW_VARS \
745 
  UINT f_op1; \
746 
  UINT f_r1; \
747 
  UINT f_uimm8; \
748 
  unsigned int length;
749 
#define EXTRACT_IFMT_CLRPSW_CODE \
750 
  length = 2; \
751 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
752 
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
753 
  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
754 
 
755 
#define EXTRACT_IFMT_BSET_VARS \
756 
  UINT f_op1; \
757 
  UINT f_bit4; \
758 
  UINT f_uimm3; \
759 
  UINT f_op2; \
760 
  UINT f_r2; \
761 
  INT f_simm16; \
762 
  unsigned int length;
763 
#define EXTRACT_IFMT_BSET_CODE \
764 
  length = 4; \
765 
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
766 
  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
767 
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
768 
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
769 
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
770 
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
771 
 
772 
#define EXTRACT_IFMT_BTST_VARS \
773 
  UINT f_op1; \
774 
  UINT f_bit4; \
775 
  UINT f_uimm3; \
776 
  UINT f_op2; \
777 
  UINT f_r2; \
778 
  unsigned int length;
779 
#define EXTRACT_IFMT_BTST_CODE \
780 
  length = 2; \
781 
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
782 
  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
783 
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
784 
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
785 
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
786 
 
787 
/* Queued output values of an instruction.  */
788 
 
789 
struct parexec {
790 
  union {
791 
    struct { /* empty sformat for unspecified field list */
792 
      int empty;
793 
    } sfmt_empty;
794 
    struct { /* e.g. add $dr,$sr */
795 
      SI dr;
796 
    } sfmt_add;
797 
    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
798 
      SI dr;
799 
    } sfmt_add3;
800 
    struct { /* e.g. and3 $dr,$sr,$uimm16 */
801 
      SI dr;
802 
    } sfmt_and3;
803 
    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
804 
      SI dr;
805 
    } sfmt_or3;
806 
    struct { /* e.g. addi $dr,$simm8 */
807 
      SI dr;
808 
    } sfmt_addi;
809 
    struct { /* e.g. addv $dr,$sr */
810 
      BI condbit;
811 
      SI dr;
812 
    } sfmt_addv;
813 
    struct { /* e.g. addv3 $dr,$sr,$simm16 */
814 
      BI condbit;
815 
      SI dr;
816 
    } sfmt_addv3;
817 
    struct { /* e.g. addx $dr,$sr */
818 
      BI condbit;
819 
      SI dr;
820 
    } sfmt_addx;
821 
    struct { /* e.g. bc.s $disp8 */
822 
      USI pc;
823 
    } sfmt_bc8;
824 
    struct { /* e.g. bc.l $disp24 */
825 
      USI pc;
826 
    } sfmt_bc24;
827 
    struct { /* e.g. beq $src1,$src2,$disp16 */
828 
      USI pc;
829 
    } sfmt_beq;
830 
    struct { /* e.g. beqz $src2,$disp16 */
831 
      USI pc;
832 
    } sfmt_beqz;
833 
    struct { /* e.g. bl.s $disp8 */
834 
      SI h_gr_SI_14;
835 
      USI pc;
836 
    } sfmt_bl8;
837 
    struct { /* e.g. bl.l $disp24 */
838 
      SI h_gr_SI_14;
839 
      USI pc;
840 
    } sfmt_bl24;
841 
    struct { /* e.g. bcl.s $disp8 */
842 
      SI h_gr_SI_14;
843 
      USI pc;
844 
    } sfmt_bcl8;
845 
    struct { /* e.g. bcl.l $disp24 */
846 
      SI h_gr_SI_14;
847 
      USI pc;
848 
    } sfmt_bcl24;
849 
    struct { /* e.g. bra.s $disp8 */
850 
      USI pc;
851 
    } sfmt_bra8;
852 
    struct { /* e.g. bra.l $disp24 */
853 
      USI pc;
854 
    } sfmt_bra24;
855 
    struct { /* e.g. cmp $src1,$src2 */
856 
      BI condbit;
857 
    } sfmt_cmp;
858 
    struct { /* e.g. cmpi $src2,$simm16 */
859 
      BI condbit;
860 
    } sfmt_cmpi;
861 
    struct { /* e.g. cmpz $src2 */
862 
      BI condbit;
863 
    } sfmt_cmpz;
864 
    struct { /* e.g. div $dr,$sr */
865 
      SI dr;
866 
    } sfmt_div;
867 
    struct { /* e.g. jc $sr */
868 
      USI pc;
869 
    } sfmt_jc;
870 
    struct { /* e.g. jl $sr */
871 
      SI h_gr_SI_14;
872 
      USI pc;
873 
    } sfmt_jl;
874 
    struct { /* e.g. jmp $sr */
875 
      USI pc;
876 
    } sfmt_jmp;
877 
    struct { /* e.g. ld $dr,@$sr */
878 
      SI dr;
879 
    } sfmt_ld;
880 
    struct { /* e.g. ld $dr,@($slo16,$sr) */
881 
      SI dr;
882 
    } sfmt_ld_d;
883 
    struct { /* e.g. ldb $dr,@$sr */
884 
      SI dr;
885 
    } sfmt_ldb;
886 
    struct { /* e.g. ldb $dr,@($slo16,$sr) */
887 
      SI dr;
888 
    } sfmt_ldb_d;
889 
    struct { /* e.g. ldh $dr,@$sr */
890 
      SI dr;
891 
    } sfmt_ldh;
892 
    struct { /* e.g. ldh $dr,@($slo16,$sr) */
893 
      SI dr;
894 
    } sfmt_ldh_d;
895 
    struct { /* e.g. ld $dr,@$sr+ */
896 
      SI dr;
897 
      SI sr;
898 
    } sfmt_ld_plus;
899 
    struct { /* e.g. ld24 $dr,$uimm24 */
900 
      SI dr;
901 
    } sfmt_ld24;
902 
    struct { /* e.g. ldi8 $dr,$simm8 */
903 
      SI dr;
904 
    } sfmt_ldi8;
905 
    struct { /* e.g. ldi16 $dr,$hash$slo16 */
906 
      SI dr;
907 
    } sfmt_ldi16;
908 
    struct { /* e.g. lock $dr,@$sr */
909 
      SI dr;
910 
      BI h_lock_BI;
911 
    } sfmt_lock;
912 
    struct { /* e.g. machi $src1,$src2,$acc */
913 
      DI acc;
914 
    } sfmt_machi_a;
915 
    struct { /* e.g. mulhi $src1,$src2,$acc */
916 
      DI acc;
917 
    } sfmt_mulhi_a;
918 
    struct { /* e.g. mv $dr,$sr */
919 
      SI dr;
920 
    } sfmt_mv;
921 
    struct { /* e.g. mvfachi $dr,$accs */
922 
      SI dr;
923 
    } sfmt_mvfachi_a;
924 
    struct { /* e.g. mvfc $dr,$scr */
925 
      SI dr;
926 
    } sfmt_mvfc;
927 
    struct { /* e.g. mvtachi $src1,$accs */
928 
      DI accs;
929 
    } sfmt_mvtachi_a;
930 
    struct { /* e.g. mvtc $sr,$dcr */
931 
      USI dcr;
932 
    } sfmt_mvtc;
933 
    struct { /* e.g. nop */
934 
      int empty;
935 
    } sfmt_nop;
936 
    struct { /* e.g. rac $accd,$accs,$imm1 */
937 
      DI accd;
938 
    } sfmt_rac_dsi;
939 
    struct { /* e.g. rte */
940 
      UQI h_bpsw_UQI;
941 
      USI h_cr_USI_6;
942 
      UQI h_psw_UQI;
943 
      USI pc;
944 
    } sfmt_rte;
945 
    struct { /* e.g. seth $dr,$hash$hi16 */
946 
      SI dr;
947 
    } sfmt_seth;
948 
    struct { /* e.g. sll3 $dr,$sr,$simm16 */
949 
      SI dr;
950 
    } sfmt_sll3;
951 
    struct { /* e.g. slli $dr,$uimm5 */
952 
      SI dr;
953 
    } sfmt_slli;
954 
    struct { /* e.g. st $src1,@$src2 */
955 
      SI h_memory_SI_src2;
956 
      USI h_memory_SI_src2_idx;
957 
    } sfmt_st;
958 
    struct { /* e.g. st $src1,@($slo16,$src2) */
959 
      SI h_memory_SI_add__SI_src2_slo16;
960 
      USI h_memory_SI_add__SI_src2_slo16_idx;
961 
    } sfmt_st_d;
962 
    struct { /* e.g. stb $src1,@$src2 */
963 
      QI h_memory_QI_src2;
964 
      USI h_memory_QI_src2_idx;
965 
    } sfmt_stb;
966 
    struct { /* e.g. stb $src1,@($slo16,$src2) */
967 
      QI h_memory_QI_add__SI_src2_slo16;
968 
      USI h_memory_QI_add__SI_src2_slo16_idx;
969 
    } sfmt_stb_d;
970 
    struct { /* e.g. sth $src1,@$src2 */
971 
      HI h_memory_HI_src2;
972 
      USI h_memory_HI_src2_idx;
973 
    } sfmt_sth;
974 
    struct { /* e.g. sth $src1,@($slo16,$src2) */
975 
      HI h_memory_HI_add__SI_src2_slo16;
976 
      USI h_memory_HI_add__SI_src2_slo16_idx;
977 
    } sfmt_sth_d;
978 
    struct { /* e.g. st $src1,@+$src2 */
979 
      SI h_memory_SI_new_src2;
980 
      USI h_memory_SI_new_src2_idx;
981 
      SI src2;
982 
    } sfmt_st_plus;
983 
    struct { /* e.g. sth $src1,@$src2+ */
984 
      HI h_memory_HI_new_src2;
985 
      USI h_memory_HI_new_src2_idx;
986 
      SI src2;
987 
    } sfmt_sth_plus;
988 
    struct { /* e.g. stb $src1,@$src2+ */
989 
      QI h_memory_QI_new_src2;
990 
      USI h_memory_QI_new_src2_idx;
991 
      SI src2;
992 
    } sfmt_stb_plus;
993 
    struct { /* e.g. trap $uimm4 */
994 
      UQI h_bbpsw_UQI;
995 
      UQI h_bpsw_UQI;
996 
      USI h_cr_USI_14;
997 
      USI h_cr_USI_6;
998 
      UQI h_psw_UQI;
999 
      USI pc;
1000 
    } sfmt_trap;
1001 
    struct { /* e.g. unlock $src1,@$src2 */
1002 
      BI h_lock_BI;
1003 
      SI h_memory_SI_src2;
1004 
      USI h_memory_SI_src2_idx;
1005 
    } sfmt_unlock;
1006 
    struct { /* e.g. satb $dr,$sr */
1007 
      SI dr;
1008 
    } sfmt_satb;
1009 
    struct { /* e.g. sat $dr,$sr */
1010 
      SI dr;
1011 
    } sfmt_sat;
1012 
    struct { /* e.g. sadd */
1013 
      DI h_accums_DI_0;
1014 
    } sfmt_sadd;
1015 
    struct { /* e.g. macwu1 $src1,$src2 */
1016 
      DI h_accums_DI_1;
1017 
    } sfmt_macwu1;
1018 
    struct { /* e.g. msblo $src1,$src2 */
1019 
      DI accum;
1020 
    } sfmt_msblo;
1021 
    struct { /* e.g. mulwu1 $src1,$src2 */
1022 
      DI h_accums_DI_1;
1023 
    } sfmt_mulwu1;
1024 
    struct { /* e.g. sc */
1025 
      int empty;
1026 
    } sfmt_sc;
1027 
    struct { /* e.g. clrpsw $uimm8 */
1028 
      USI h_cr_USI_0;
1029 
    } sfmt_clrpsw;
1030 
    struct { /* e.g. setpsw $uimm8 */
1031 
      USI h_cr_USI_0;
1032 
    } sfmt_setpsw;
1033 
    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
1034 
      QI h_memory_QI_add__SI_sr_slo16;
1035 
      USI h_memory_QI_add__SI_sr_slo16_idx;
1036 
    } sfmt_bset;
1037 
    struct { /* e.g. btst $uimm3,$sr */
1038 
      BI condbit;
1039 
    } sfmt_btst;
1040 
  } operands;
1041 
  /* For conditionally written operands, bitmask of which ones were.  */
1042 
  int written;
1043 
};
1044 
 
1045 
/* Collection of various things for the trace handler to use.  */
1046 
 
1047 
typedef struct trace_record {
1048 
  IADDR pc;
1049 
  /* FIXME:wip */
1050 
} TRACE_RECORD;
1051 
 
1052 
#endif /* CPU_M32RXF_H */

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