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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [m32r/] [model.c] - Blame information for rev 842

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1 227 jeremybenn
/* Simulator model support for m32rbf.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#define WANT_CPU m32rbf
26
#define WANT_CPU_M32RBF
27
 
28
#include "sim-main.h"
29
 
30
/* The profiling data is recorded here, but is accessed via the profiling
31
   mechanism.  After all, this is information for profiling.  */
32
 
33
#if WITH_PROFILE_MODEL_P
34
 
35
/* Model handlers for each insn.  */
36
 
37
static int
38
model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
39
{
40
#define FLD(f) abuf->fields.sfmt_add.f
41
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42
  const IDESC * UNUSED idesc = abuf->idesc;
43
  int cycles = 0;
44
  {
45
    int referenced = 0;
46
    int UNUSED insn_referenced = abuf->written;
47
    INT in_sr = -1;
48
    INT in_dr = -1;
49
    INT out_dr = -1;
50
    in_sr = FLD (in_sr);
51
    in_dr = FLD (in_dr);
52
    out_dr = FLD (out_dr);
53
    referenced |= 1 << 0;
54
    referenced |= 1 << 1;
55
    referenced |= 1 << 2;
56
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
57
  }
58
  return cycles;
59
#undef FLD
60
}
61
 
62
static int
63
model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
64
{
65
#define FLD(f) abuf->fields.sfmt_add3.f
66
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
67
  const IDESC * UNUSED idesc = abuf->idesc;
68
  int cycles = 0;
69
  {
70
    int referenced = 0;
71
    int UNUSED insn_referenced = abuf->written;
72
    INT in_sr = -1;
73
    INT in_dr = -1;
74
    INT out_dr = -1;
75
    in_sr = FLD (in_sr);
76
    out_dr = FLD (out_dr);
77
    referenced |= 1 << 0;
78
    referenced |= 1 << 2;
79
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
80
  }
81
  return cycles;
82
#undef FLD
83
}
84
 
85
static int
86
model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
87
{
88
#define FLD(f) abuf->fields.sfmt_add.f
89
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
90
  const IDESC * UNUSED idesc = abuf->idesc;
91
  int cycles = 0;
92
  {
93
    int referenced = 0;
94
    int UNUSED insn_referenced = abuf->written;
95
    INT in_sr = -1;
96
    INT in_dr = -1;
97
    INT out_dr = -1;
98
    in_sr = FLD (in_sr);
99
    in_dr = FLD (in_dr);
100
    out_dr = FLD (out_dr);
101
    referenced |= 1 << 0;
102
    referenced |= 1 << 1;
103
    referenced |= 1 << 2;
104
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
105
  }
106
  return cycles;
107
#undef FLD
108
}
109
 
110
static int
111
model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
112
{
113
#define FLD(f) abuf->fields.sfmt_and3.f
114
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
115
  const IDESC * UNUSED idesc = abuf->idesc;
116
  int cycles = 0;
117
  {
118
    int referenced = 0;
119
    int UNUSED insn_referenced = abuf->written;
120
    INT in_sr = -1;
121
    INT in_dr = -1;
122
    INT out_dr = -1;
123
    in_sr = FLD (in_sr);
124
    out_dr = FLD (out_dr);
125
    referenced |= 1 << 0;
126
    referenced |= 1 << 2;
127
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
128
  }
129
  return cycles;
130
#undef FLD
131
}
132
 
133
static int
134
model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
135
{
136
#define FLD(f) abuf->fields.sfmt_add.f
137
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
138
  const IDESC * UNUSED idesc = abuf->idesc;
139
  int cycles = 0;
140
  {
141
    int referenced = 0;
142
    int UNUSED insn_referenced = abuf->written;
143
    INT in_sr = -1;
144
    INT in_dr = -1;
145
    INT out_dr = -1;
146
    in_sr = FLD (in_sr);
147
    in_dr = FLD (in_dr);
148
    out_dr = FLD (out_dr);
149
    referenced |= 1 << 0;
150
    referenced |= 1 << 1;
151
    referenced |= 1 << 2;
152
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
153
  }
154
  return cycles;
155
#undef FLD
156
}
157
 
158
static int
159
model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
160
{
161
#define FLD(f) abuf->fields.sfmt_and3.f
162
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
163
  const IDESC * UNUSED idesc = abuf->idesc;
164
  int cycles = 0;
165
  {
166
    int referenced = 0;
167
    int UNUSED insn_referenced = abuf->written;
168
    INT in_sr = -1;
169
    INT in_dr = -1;
170
    INT out_dr = -1;
171
    in_sr = FLD (in_sr);
172
    out_dr = FLD (out_dr);
173
    referenced |= 1 << 0;
174
    referenced |= 1 << 2;
175
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
176
  }
177
  return cycles;
178
#undef FLD
179
}
180
 
181
static int
182
model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
183
{
184
#define FLD(f) abuf->fields.sfmt_add.f
185
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
186
  const IDESC * UNUSED idesc = abuf->idesc;
187
  int cycles = 0;
188
  {
189
    int referenced = 0;
190
    int UNUSED insn_referenced = abuf->written;
191
    INT in_sr = -1;
192
    INT in_dr = -1;
193
    INT out_dr = -1;
194
    in_sr = FLD (in_sr);
195
    in_dr = FLD (in_dr);
196
    out_dr = FLD (out_dr);
197
    referenced |= 1 << 0;
198
    referenced |= 1 << 1;
199
    referenced |= 1 << 2;
200
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
201
  }
202
  return cycles;
203
#undef FLD
204
}
205
 
206
static int
207
model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
208
{
209
#define FLD(f) abuf->fields.sfmt_and3.f
210
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
211
  const IDESC * UNUSED idesc = abuf->idesc;
212
  int cycles = 0;
213
  {
214
    int referenced = 0;
215
    int UNUSED insn_referenced = abuf->written;
216
    INT in_sr = -1;
217
    INT in_dr = -1;
218
    INT out_dr = -1;
219
    in_sr = FLD (in_sr);
220
    out_dr = FLD (out_dr);
221
    referenced |= 1 << 0;
222
    referenced |= 1 << 2;
223
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
224
  }
225
  return cycles;
226
#undef FLD
227
}
228
 
229
static int
230
model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
231
{
232
#define FLD(f) abuf->fields.sfmt_addi.f
233
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
234
  const IDESC * UNUSED idesc = abuf->idesc;
235
  int cycles = 0;
236
  {
237
    int referenced = 0;
238
    int UNUSED insn_referenced = abuf->written;
239
    INT in_sr = -1;
240
    INT in_dr = -1;
241
    INT out_dr = -1;
242
    in_dr = FLD (in_dr);
243
    out_dr = FLD (out_dr);
244
    referenced |= 1 << 1;
245
    referenced |= 1 << 2;
246
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
247
  }
248
  return cycles;
249
#undef FLD
250
}
251
 
252
static int
253
model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
254
{
255
#define FLD(f) abuf->fields.sfmt_add.f
256
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
257
  const IDESC * UNUSED idesc = abuf->idesc;
258
  int cycles = 0;
259
  {
260
    int referenced = 0;
261
    int UNUSED insn_referenced = abuf->written;
262
    INT in_sr = -1;
263
    INT in_dr = -1;
264
    INT out_dr = -1;
265
    in_sr = FLD (in_sr);
266
    in_dr = FLD (in_dr);
267
    out_dr = FLD (out_dr);
268
    referenced |= 1 << 0;
269
    referenced |= 1 << 1;
270
    referenced |= 1 << 2;
271
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
272
  }
273
  return cycles;
274
#undef FLD
275
}
276
 
277
static int
278
model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
279
{
280
#define FLD(f) abuf->fields.sfmt_add3.f
281
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
282
  const IDESC * UNUSED idesc = abuf->idesc;
283
  int cycles = 0;
284
  {
285
    int referenced = 0;
286
    int UNUSED insn_referenced = abuf->written;
287
    INT in_sr = -1;
288
    INT in_dr = -1;
289
    INT out_dr = -1;
290
    in_sr = FLD (in_sr);
291
    out_dr = FLD (out_dr);
292
    referenced |= 1 << 0;
293
    referenced |= 1 << 2;
294
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
295
  }
296
  return cycles;
297
#undef FLD
298
}
299
 
300
static int
301
model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
302
{
303
#define FLD(f) abuf->fields.sfmt_add.f
304
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
305
  const IDESC * UNUSED idesc = abuf->idesc;
306
  int cycles = 0;
307
  {
308
    int referenced = 0;
309
    int UNUSED insn_referenced = abuf->written;
310
    INT in_sr = -1;
311
    INT in_dr = -1;
312
    INT out_dr = -1;
313
    in_sr = FLD (in_sr);
314
    in_dr = FLD (in_dr);
315
    out_dr = FLD (out_dr);
316
    referenced |= 1 << 0;
317
    referenced |= 1 << 1;
318
    referenced |= 1 << 2;
319
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
320
  }
321
  return cycles;
322
#undef FLD
323
}
324
 
325
static int
326
model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
327
{
328
#define FLD(f) abuf->fields.sfmt_bl8.f
329
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
330
  const IDESC * UNUSED idesc = abuf->idesc;
331
  int cycles = 0;
332
  {
333
    int referenced = 0;
334
    int UNUSED insn_referenced = abuf->written;
335
    INT in_sr = -1;
336
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
337
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
338
  }
339
  return cycles;
340
#undef FLD
341
}
342
 
343
static int
344
model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
345
{
346
#define FLD(f) abuf->fields.sfmt_bl24.f
347
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
348
  const IDESC * UNUSED idesc = abuf->idesc;
349
  int cycles = 0;
350
  {
351
    int referenced = 0;
352
    int UNUSED insn_referenced = abuf->written;
353
    INT in_sr = -1;
354
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
355
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
356
  }
357
  return cycles;
358
#undef FLD
359
}
360
 
361
static int
362
model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
363
{
364
#define FLD(f) abuf->fields.sfmt_beq.f
365
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
366
  const IDESC * UNUSED idesc = abuf->idesc;
367
  int cycles = 0;
368
  {
369
    int referenced = 0;
370
    int UNUSED insn_referenced = abuf->written;
371
    INT in_sr = -1;
372
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
373
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
374
  }
375
  {
376
    int referenced = 0;
377
    int UNUSED insn_referenced = abuf->written;
378
    INT in_src1 = -1;
379
    INT in_src2 = -1;
380
    in_src1 = FLD (in_src1);
381
    in_src2 = FLD (in_src2);
382
    referenced |= 1 << 0;
383
    referenced |= 1 << 1;
384
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
385
  }
386
  return cycles;
387
#undef FLD
388
}
389
 
390
static int
391
model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
392
{
393
#define FLD(f) abuf->fields.sfmt_beq.f
394
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
395
  const IDESC * UNUSED idesc = abuf->idesc;
396
  int cycles = 0;
397
  {
398
    int referenced = 0;
399
    int UNUSED insn_referenced = abuf->written;
400
    INT in_sr = -1;
401
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
402
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
403
  }
404
  {
405
    int referenced = 0;
406
    int UNUSED insn_referenced = abuf->written;
407
    INT in_src1 = -1;
408
    INT in_src2 = -1;
409
    in_src2 = FLD (in_src2);
410
    referenced |= 1 << 1;
411
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
412
  }
413
  return cycles;
414
#undef FLD
415
}
416
 
417
static int
418
model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
419
{
420
#define FLD(f) abuf->fields.sfmt_beq.f
421
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
422
  const IDESC * UNUSED idesc = abuf->idesc;
423
  int cycles = 0;
424
  {
425
    int referenced = 0;
426
    int UNUSED insn_referenced = abuf->written;
427
    INT in_sr = -1;
428
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
429
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
430
  }
431
  {
432
    int referenced = 0;
433
    int UNUSED insn_referenced = abuf->written;
434
    INT in_src1 = -1;
435
    INT in_src2 = -1;
436
    in_src2 = FLD (in_src2);
437
    referenced |= 1 << 1;
438
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
439
  }
440
  return cycles;
441
#undef FLD
442
}
443
 
444
static int
445
model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
446
{
447
#define FLD(f) abuf->fields.sfmt_beq.f
448
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
449
  const IDESC * UNUSED idesc = abuf->idesc;
450
  int cycles = 0;
451
  {
452
    int referenced = 0;
453
    int UNUSED insn_referenced = abuf->written;
454
    INT in_sr = -1;
455
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
456
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
457
  }
458
  {
459
    int referenced = 0;
460
    int UNUSED insn_referenced = abuf->written;
461
    INT in_src1 = -1;
462
    INT in_src2 = -1;
463
    in_src2 = FLD (in_src2);
464
    referenced |= 1 << 1;
465
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
466
  }
467
  return cycles;
468
#undef FLD
469
}
470
 
471
static int
472
model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
473
{
474
#define FLD(f) abuf->fields.sfmt_beq.f
475
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
476
  const IDESC * UNUSED idesc = abuf->idesc;
477
  int cycles = 0;
478
  {
479
    int referenced = 0;
480
    int UNUSED insn_referenced = abuf->written;
481
    INT in_sr = -1;
482
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
483
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
484
  }
485
  {
486
    int referenced = 0;
487
    int UNUSED insn_referenced = abuf->written;
488
    INT in_src1 = -1;
489
    INT in_src2 = -1;
490
    in_src2 = FLD (in_src2);
491
    referenced |= 1 << 1;
492
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
493
  }
494
  return cycles;
495
#undef FLD
496
}
497
 
498
static int
499
model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
500
{
501
#define FLD(f) abuf->fields.sfmt_beq.f
502
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
503
  const IDESC * UNUSED idesc = abuf->idesc;
504
  int cycles = 0;
505
  {
506
    int referenced = 0;
507
    int UNUSED insn_referenced = abuf->written;
508
    INT in_sr = -1;
509
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
510
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
511
  }
512
  {
513
    int referenced = 0;
514
    int UNUSED insn_referenced = abuf->written;
515
    INT in_src1 = -1;
516
    INT in_src2 = -1;
517
    in_src2 = FLD (in_src2);
518
    referenced |= 1 << 1;
519
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
520
  }
521
  return cycles;
522
#undef FLD
523
}
524
 
525
static int
526
model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
527
{
528
#define FLD(f) abuf->fields.sfmt_beq.f
529
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
530
  const IDESC * UNUSED idesc = abuf->idesc;
531
  int cycles = 0;
532
  {
533
    int referenced = 0;
534
    int UNUSED insn_referenced = abuf->written;
535
    INT in_sr = -1;
536
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
537
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
538
  }
539
  {
540
    int referenced = 0;
541
    int UNUSED insn_referenced = abuf->written;
542
    INT in_src1 = -1;
543
    INT in_src2 = -1;
544
    in_src2 = FLD (in_src2);
545
    referenced |= 1 << 1;
546
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
547
  }
548
  return cycles;
549
#undef FLD
550
}
551
 
552
static int
553
model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
554
{
555
#define FLD(f) abuf->fields.sfmt_bl8.f
556
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
557
  const IDESC * UNUSED idesc = abuf->idesc;
558
  int cycles = 0;
559
  {
560
    int referenced = 0;
561
    int UNUSED insn_referenced = abuf->written;
562
    INT in_sr = -1;
563
    referenced |= 1 << 1;
564
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
565
  }
566
  return cycles;
567
#undef FLD
568
}
569
 
570
static int
571
model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
572
{
573
#define FLD(f) abuf->fields.sfmt_bl24.f
574
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
575
  const IDESC * UNUSED idesc = abuf->idesc;
576
  int cycles = 0;
577
  {
578
    int referenced = 0;
579
    int UNUSED insn_referenced = abuf->written;
580
    INT in_sr = -1;
581
    referenced |= 1 << 1;
582
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
583
  }
584
  return cycles;
585
#undef FLD
586
}
587
 
588
static int
589
model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
590
{
591
#define FLD(f) abuf->fields.sfmt_bl8.f
592
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
593
  const IDESC * UNUSED idesc = abuf->idesc;
594
  int cycles = 0;
595
  {
596
    int referenced = 0;
597
    int UNUSED insn_referenced = abuf->written;
598
    INT in_sr = -1;
599
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
600
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
601
  }
602
  return cycles;
603
#undef FLD
604
}
605
 
606
static int
607
model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
608
{
609
#define FLD(f) abuf->fields.sfmt_bl24.f
610
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
611
  const IDESC * UNUSED idesc = abuf->idesc;
612
  int cycles = 0;
613
  {
614
    int referenced = 0;
615
    int UNUSED insn_referenced = abuf->written;
616
    INT in_sr = -1;
617
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
618
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
619
  }
620
  return cycles;
621
#undef FLD
622
}
623
 
624
static int
625
model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
626
{
627
#define FLD(f) abuf->fields.sfmt_beq.f
628
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
629
  const IDESC * UNUSED idesc = abuf->idesc;
630
  int cycles = 0;
631
  {
632
    int referenced = 0;
633
    int UNUSED insn_referenced = abuf->written;
634
    INT in_sr = -1;
635
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
636
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
637
  }
638
  {
639
    int referenced = 0;
640
    int UNUSED insn_referenced = abuf->written;
641
    INT in_src1 = -1;
642
    INT in_src2 = -1;
643
    in_src1 = FLD (in_src1);
644
    in_src2 = FLD (in_src2);
645
    referenced |= 1 << 0;
646
    referenced |= 1 << 1;
647
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
648
  }
649
  return cycles;
650
#undef FLD
651
}
652
 
653
static int
654
model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
655
{
656
#define FLD(f) abuf->fields.sfmt_bl8.f
657
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
658
  const IDESC * UNUSED idesc = abuf->idesc;
659
  int cycles = 0;
660
  {
661
    int referenced = 0;
662
    int UNUSED insn_referenced = abuf->written;
663
    INT in_sr = -1;
664
    referenced |= 1 << 1;
665
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
666
  }
667
  return cycles;
668
#undef FLD
669
}
670
 
671
static int
672
model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
673
{
674
#define FLD(f) abuf->fields.sfmt_bl24.f
675
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
676
  const IDESC * UNUSED idesc = abuf->idesc;
677
  int cycles = 0;
678
  {
679
    int referenced = 0;
680
    int UNUSED insn_referenced = abuf->written;
681
    INT in_sr = -1;
682
    referenced |= 1 << 1;
683
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
684
  }
685
  return cycles;
686
#undef FLD
687
}
688
 
689
static int
690
model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
691
{
692
#define FLD(f) abuf->fields.sfmt_st_plus.f
693
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
694
  const IDESC * UNUSED idesc = abuf->idesc;
695
  int cycles = 0;
696
  {
697
    int referenced = 0;
698
    int UNUSED insn_referenced = abuf->written;
699
    INT in_src1 = -1;
700
    INT in_src2 = -1;
701
    in_src1 = FLD (in_src1);
702
    in_src2 = FLD (in_src2);
703
    referenced |= 1 << 0;
704
    referenced |= 1 << 1;
705
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
706
  }
707
  return cycles;
708
#undef FLD
709
}
710
 
711
static int
712
model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
713
{
714
#define FLD(f) abuf->fields.sfmt_st_d.f
715
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
716
  const IDESC * UNUSED idesc = abuf->idesc;
717
  int cycles = 0;
718
  {
719
    int referenced = 0;
720
    int UNUSED insn_referenced = abuf->written;
721
    INT in_src1 = -1;
722
    INT in_src2 = -1;
723
    in_src2 = FLD (in_src2);
724
    referenced |= 1 << 1;
725
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
726
  }
727
  return cycles;
728
#undef FLD
729
}
730
 
731
static int
732
model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
733
{
734
#define FLD(f) abuf->fields.sfmt_st_plus.f
735
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
736
  const IDESC * UNUSED idesc = abuf->idesc;
737
  int cycles = 0;
738
  {
739
    int referenced = 0;
740
    int UNUSED insn_referenced = abuf->written;
741
    INT in_src1 = -1;
742
    INT in_src2 = -1;
743
    in_src1 = FLD (in_src1);
744
    in_src2 = FLD (in_src2);
745
    referenced |= 1 << 0;
746
    referenced |= 1 << 1;
747
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
748
  }
749
  return cycles;
750
#undef FLD
751
}
752
 
753
static int
754
model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
755
{
756
#define FLD(f) abuf->fields.sfmt_st_d.f
757
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
758
  const IDESC * UNUSED idesc = abuf->idesc;
759
  int cycles = 0;
760
  {
761
    int referenced = 0;
762
    int UNUSED insn_referenced = abuf->written;
763
    INT in_src1 = -1;
764
    INT in_src2 = -1;
765
    in_src2 = FLD (in_src2);
766
    referenced |= 1 << 1;
767
    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
768
  }
769
  return cycles;
770
#undef FLD
771
}
772
 
773
static int
774
model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
775
{
776
#define FLD(f) abuf->fields.sfmt_add.f
777
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
778
  const IDESC * UNUSED idesc = abuf->idesc;
779
  int cycles = 0;
780
  {
781
    int referenced = 0;
782
    int UNUSED insn_referenced = abuf->written;
783
    INT in_sr = -1;
784
    INT in_dr = -1;
785
    INT out_dr = -1;
786
    in_sr = FLD (in_sr);
787
    in_dr = FLD (in_dr);
788
    out_dr = FLD (out_dr);
789
    referenced |= 1 << 0;
790
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
791
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
792
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
793
  }
794
  return cycles;
795
#undef FLD
796
}
797
 
798
static int
799
model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
800
{
801
#define FLD(f) abuf->fields.sfmt_add.f
802
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
803
  const IDESC * UNUSED idesc = abuf->idesc;
804
  int cycles = 0;
805
  {
806
    int referenced = 0;
807
    int UNUSED insn_referenced = abuf->written;
808
    INT in_sr = -1;
809
    INT in_dr = -1;
810
    INT out_dr = -1;
811
    in_sr = FLD (in_sr);
812
    in_dr = FLD (in_dr);
813
    out_dr = FLD (out_dr);
814
    referenced |= 1 << 0;
815
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
816
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
817
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
818
  }
819
  return cycles;
820
#undef FLD
821
}
822
 
823
static int
824
model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
825
{
826
#define FLD(f) abuf->fields.sfmt_add.f
827
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
828
  const IDESC * UNUSED idesc = abuf->idesc;
829
  int cycles = 0;
830
  {
831
    int referenced = 0;
832
    int UNUSED insn_referenced = abuf->written;
833
    INT in_sr = -1;
834
    INT in_dr = -1;
835
    INT out_dr = -1;
836
    in_sr = FLD (in_sr);
837
    in_dr = FLD (in_dr);
838
    out_dr = FLD (out_dr);
839
    referenced |= 1 << 0;
840
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
841
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
842
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
843
  }
844
  return cycles;
845
#undef FLD
846
}
847
 
848
static int
849
model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
850
{
851
#define FLD(f) abuf->fields.sfmt_add.f
852
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
853
  const IDESC * UNUSED idesc = abuf->idesc;
854
  int cycles = 0;
855
  {
856
    int referenced = 0;
857
    int UNUSED insn_referenced = abuf->written;
858
    INT in_sr = -1;
859
    INT in_dr = -1;
860
    INT out_dr = -1;
861
    in_sr = FLD (in_sr);
862
    in_dr = FLD (in_dr);
863
    out_dr = FLD (out_dr);
864
    referenced |= 1 << 0;
865
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
866
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
867
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
868
  }
869
  return cycles;
870
#undef FLD
871
}
872
 
873
static int
874
model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
875
{
876
#define FLD(f) abuf->fields.sfmt_jl.f
877
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
878
  const IDESC * UNUSED idesc = abuf->idesc;
879
  int cycles = 0;
880
  {
881
    int referenced = 0;
882
    int UNUSED insn_referenced = abuf->written;
883
    INT in_sr = -1;
884
    in_sr = FLD (in_sr);
885
    referenced |= 1 << 0;
886
    referenced |= 1 << 1;
887
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
888
  }
889
  return cycles;
890
#undef FLD
891
}
892
 
893
static int
894
model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
895
{
896
#define FLD(f) abuf->fields.sfmt_jl.f
897
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
898
  const IDESC * UNUSED idesc = abuf->idesc;
899
  int cycles = 0;
900
  {
901
    int referenced = 0;
902
    int UNUSED insn_referenced = abuf->written;
903
    INT in_sr = -1;
904
    in_sr = FLD (in_sr);
905
    referenced |= 1 << 0;
906
    referenced |= 1 << 1;
907
    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
908
  }
909
  return cycles;
910
#undef FLD
911
}
912
 
913
static int
914
model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
915
{
916
#define FLD(f) abuf->fields.sfmt_ld_plus.f
917
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
918
  const IDESC * UNUSED idesc = abuf->idesc;
919
  int cycles = 0;
920
  {
921
    int referenced = 0;
922
    int UNUSED insn_referenced = abuf->written;
923
    INT in_sr = 0;
924
    INT out_dr = 0;
925
    in_sr = FLD (in_sr);
926
    out_dr = FLD (out_dr);
927
    referenced |= 1 << 0;
928
    referenced |= 1 << 1;
929
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
930
  }
931
  return cycles;
932
#undef FLD
933
}
934
 
935
static int
936
model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
937
{
938
#define FLD(f) abuf->fields.sfmt_add3.f
939
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
940
  const IDESC * UNUSED idesc = abuf->idesc;
941
  int cycles = 0;
942
  {
943
    int referenced = 0;
944
    int UNUSED insn_referenced = abuf->written;
945
    INT in_sr = 0;
946
    INT out_dr = 0;
947
    in_sr = FLD (in_sr);
948
    out_dr = FLD (out_dr);
949
    referenced |= 1 << 0;
950
    referenced |= 1 << 1;
951
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
952
  }
953
  return cycles;
954
#undef FLD
955
}
956
 
957
static int
958
model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
959
{
960
#define FLD(f) abuf->fields.sfmt_ld_plus.f
961
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
962
  const IDESC * UNUSED idesc = abuf->idesc;
963
  int cycles = 0;
964
  {
965
    int referenced = 0;
966
    int UNUSED insn_referenced = abuf->written;
967
    INT in_sr = 0;
968
    INT out_dr = 0;
969
    in_sr = FLD (in_sr);
970
    out_dr = FLD (out_dr);
971
    referenced |= 1 << 0;
972
    referenced |= 1 << 1;
973
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
974
  }
975
  return cycles;
976
#undef FLD
977
}
978
 
979
static int
980
model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
981
{
982
#define FLD(f) abuf->fields.sfmt_add3.f
983
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
984
  const IDESC * UNUSED idesc = abuf->idesc;
985
  int cycles = 0;
986
  {
987
    int referenced = 0;
988
    int UNUSED insn_referenced = abuf->written;
989
    INT in_sr = 0;
990
    INT out_dr = 0;
991
    in_sr = FLD (in_sr);
992
    out_dr = FLD (out_dr);
993
    referenced |= 1 << 0;
994
    referenced |= 1 << 1;
995
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
996
  }
997
  return cycles;
998
#undef FLD
999
}
1000
 
1001
static int
1002
model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
1003
{
1004
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1005
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1006
  const IDESC * UNUSED idesc = abuf->idesc;
1007
  int cycles = 0;
1008
  {
1009
    int referenced = 0;
1010
    int UNUSED insn_referenced = abuf->written;
1011
    INT in_sr = 0;
1012
    INT out_dr = 0;
1013
    in_sr = FLD (in_sr);
1014
    out_dr = FLD (out_dr);
1015
    referenced |= 1 << 0;
1016
    referenced |= 1 << 1;
1017
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1018
  }
1019
  return cycles;
1020
#undef FLD
1021
}
1022
 
1023
static int
1024
model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1025
{
1026
#define FLD(f) abuf->fields.sfmt_add3.f
1027
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1028
  const IDESC * UNUSED idesc = abuf->idesc;
1029
  int cycles = 0;
1030
  {
1031
    int referenced = 0;
1032
    int UNUSED insn_referenced = abuf->written;
1033
    INT in_sr = 0;
1034
    INT out_dr = 0;
1035
    in_sr = FLD (in_sr);
1036
    out_dr = FLD (out_dr);
1037
    referenced |= 1 << 0;
1038
    referenced |= 1 << 1;
1039
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1040
  }
1041
  return cycles;
1042
#undef FLD
1043
}
1044
 
1045
static int
1046
model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
1047
{
1048
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1049
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1050
  const IDESC * UNUSED idesc = abuf->idesc;
1051
  int cycles = 0;
1052
  {
1053
    int referenced = 0;
1054
    int UNUSED insn_referenced = abuf->written;
1055
    INT in_sr = 0;
1056
    INT out_dr = 0;
1057
    in_sr = FLD (in_sr);
1058
    out_dr = FLD (out_dr);
1059
    referenced |= 1 << 0;
1060
    referenced |= 1 << 1;
1061
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1062
  }
1063
  return cycles;
1064
#undef FLD
1065
}
1066
 
1067
static int
1068
model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1069
{
1070
#define FLD(f) abuf->fields.sfmt_add3.f
1071
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1072
  const IDESC * UNUSED idesc = abuf->idesc;
1073
  int cycles = 0;
1074
  {
1075
    int referenced = 0;
1076
    int UNUSED insn_referenced = abuf->written;
1077
    INT in_sr = 0;
1078
    INT out_dr = 0;
1079
    in_sr = FLD (in_sr);
1080
    out_dr = FLD (out_dr);
1081
    referenced |= 1 << 0;
1082
    referenced |= 1 << 1;
1083
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1084
  }
1085
  return cycles;
1086
#undef FLD
1087
}
1088
 
1089
static int
1090
model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
1091
{
1092
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1093
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1094
  const IDESC * UNUSED idesc = abuf->idesc;
1095
  int cycles = 0;
1096
  {
1097
    int referenced = 0;
1098
    int UNUSED insn_referenced = abuf->written;
1099
    INT in_sr = 0;
1100
    INT out_dr = 0;
1101
    in_sr = FLD (in_sr);
1102
    out_dr = FLD (out_dr);
1103
    referenced |= 1 << 0;
1104
    referenced |= 1 << 1;
1105
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1106
  }
1107
  return cycles;
1108
#undef FLD
1109
}
1110
 
1111
static int
1112
model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1113
{
1114
#define FLD(f) abuf->fields.sfmt_add3.f
1115
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1116
  const IDESC * UNUSED idesc = abuf->idesc;
1117
  int cycles = 0;
1118
  {
1119
    int referenced = 0;
1120
    int UNUSED insn_referenced = abuf->written;
1121
    INT in_sr = 0;
1122
    INT out_dr = 0;
1123
    in_sr = FLD (in_sr);
1124
    out_dr = FLD (out_dr);
1125
    referenced |= 1 << 0;
1126
    referenced |= 1 << 1;
1127
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1128
  }
1129
  return cycles;
1130
#undef FLD
1131
}
1132
 
1133
static int
1134
model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1135
{
1136
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1137
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1138
  const IDESC * UNUSED idesc = abuf->idesc;
1139
  int cycles = 0;
1140
  {
1141
    int referenced = 0;
1142
    int UNUSED insn_referenced = abuf->written;
1143
    INT in_sr = 0;
1144
    INT out_dr = 0;
1145
    in_sr = FLD (in_sr);
1146
    out_dr = FLD (out_dr);
1147
    referenced |= 1 << 0;
1148
    referenced |= 1 << 1;
1149
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1150
  }
1151
  {
1152
    int referenced = 0;
1153
    int UNUSED insn_referenced = abuf->written;
1154
    INT in_sr = -1;
1155
    INT in_dr = -1;
1156
    INT out_dr = -1;
1157
    in_dr = FLD (in_sr);
1158
    out_dr = FLD (out_sr);
1159
    referenced |= 1 << 0;
1160
    referenced |= 1 << 2;
1161
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
1162
  }
1163
  return cycles;
1164
#undef FLD
1165
}
1166
 
1167
static int
1168
model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1169
{
1170
#define FLD(f) abuf->fields.sfmt_ld24.f
1171
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1172
  const IDESC * UNUSED idesc = abuf->idesc;
1173
  int cycles = 0;
1174
  {
1175
    int referenced = 0;
1176
    int UNUSED insn_referenced = abuf->written;
1177
    INT in_sr = -1;
1178
    INT in_dr = -1;
1179
    INT out_dr = -1;
1180
    out_dr = FLD (out_dr);
1181
    referenced |= 1 << 2;
1182
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1183
  }
1184
  return cycles;
1185
#undef FLD
1186
}
1187
 
1188
static int
1189
model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1190
{
1191
#define FLD(f) abuf->fields.sfmt_addi.f
1192
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1193
  const IDESC * UNUSED idesc = abuf->idesc;
1194
  int cycles = 0;
1195
  {
1196
    int referenced = 0;
1197
    int UNUSED insn_referenced = abuf->written;
1198
    INT in_sr = -1;
1199
    INT in_dr = -1;
1200
    INT out_dr = -1;
1201
    out_dr = FLD (out_dr);
1202
    referenced |= 1 << 2;
1203
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1204
  }
1205
  return cycles;
1206
#undef FLD
1207
}
1208
 
1209
static int
1210
model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1211
{
1212
#define FLD(f) abuf->fields.sfmt_add3.f
1213
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1214
  const IDESC * UNUSED idesc = abuf->idesc;
1215
  int cycles = 0;
1216
  {
1217
    int referenced = 0;
1218
    int UNUSED insn_referenced = abuf->written;
1219
    INT in_sr = -1;
1220
    INT in_dr = -1;
1221
    INT out_dr = -1;
1222
    out_dr = FLD (out_dr);
1223
    referenced |= 1 << 2;
1224
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1225
  }
1226
  return cycles;
1227
#undef FLD
1228
}
1229
 
1230
static int
1231
model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
1232
{
1233
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1234
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1235
  const IDESC * UNUSED idesc = abuf->idesc;
1236
  int cycles = 0;
1237
  {
1238
    int referenced = 0;
1239
    int UNUSED insn_referenced = abuf->written;
1240
    INT in_sr = 0;
1241
    INT out_dr = 0;
1242
    in_sr = FLD (in_sr);
1243
    out_dr = FLD (out_dr);
1244
    referenced |= 1 << 0;
1245
    referenced |= 1 << 1;
1246
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1247
  }
1248
  return cycles;
1249
#undef FLD
1250
}
1251
 
1252
static int
1253
model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
1254
{
1255
#define FLD(f) abuf->fields.sfmt_st_plus.f
1256
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1257
  const IDESC * UNUSED idesc = abuf->idesc;
1258
  int cycles = 0;
1259
  {
1260
    int referenced = 0;
1261
    int UNUSED insn_referenced = abuf->written;
1262
    INT in_src1 = -1;
1263
    INT in_src2 = -1;
1264
    in_src1 = FLD (in_src1);
1265
    in_src2 = FLD (in_src2);
1266
    referenced |= 1 << 0;
1267
    referenced |= 1 << 1;
1268
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1269
  }
1270
  return cycles;
1271
#undef FLD
1272
}
1273
 
1274
static int
1275
model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
1276
{
1277
#define FLD(f) abuf->fields.sfmt_st_plus.f
1278
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1279
  const IDESC * UNUSED idesc = abuf->idesc;
1280
  int cycles = 0;
1281
  {
1282
    int referenced = 0;
1283
    int UNUSED insn_referenced = abuf->written;
1284
    INT in_src1 = -1;
1285
    INT in_src2 = -1;
1286
    in_src1 = FLD (in_src1);
1287
    in_src2 = FLD (in_src2);
1288
    referenced |= 1 << 0;
1289
    referenced |= 1 << 1;
1290
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1291
  }
1292
  return cycles;
1293
#undef FLD
1294
}
1295
 
1296
static int
1297
model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
1298
{
1299
#define FLD(f) abuf->fields.sfmt_st_plus.f
1300
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1301
  const IDESC * UNUSED idesc = abuf->idesc;
1302
  int cycles = 0;
1303
  {
1304
    int referenced = 0;
1305
    int UNUSED insn_referenced = abuf->written;
1306
    INT in_src1 = -1;
1307
    INT in_src2 = -1;
1308
    in_src1 = FLD (in_src1);
1309
    in_src2 = FLD (in_src2);
1310
    referenced |= 1 << 0;
1311
    referenced |= 1 << 1;
1312
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1313
  }
1314
  return cycles;
1315
#undef FLD
1316
}
1317
 
1318
static int
1319
model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
1320
{
1321
#define FLD(f) abuf->fields.sfmt_st_plus.f
1322
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1323
  const IDESC * UNUSED idesc = abuf->idesc;
1324
  int cycles = 0;
1325
  {
1326
    int referenced = 0;
1327
    int UNUSED insn_referenced = abuf->written;
1328
    INT in_src1 = -1;
1329
    INT in_src2 = -1;
1330
    in_src1 = FLD (in_src1);
1331
    in_src2 = FLD (in_src2);
1332
    referenced |= 1 << 0;
1333
    referenced |= 1 << 1;
1334
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1335
  }
1336
  return cycles;
1337
#undef FLD
1338
}
1339
 
1340
static int
1341
model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
1342
{
1343
#define FLD(f) abuf->fields.sfmt_add.f
1344
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1345
  const IDESC * UNUSED idesc = abuf->idesc;
1346
  int cycles = 0;
1347
  {
1348
    int referenced = 0;
1349
    int UNUSED insn_referenced = abuf->written;
1350
    INT in_sr = -1;
1351
    INT in_dr = -1;
1352
    INT out_dr = -1;
1353
    in_sr = FLD (in_sr);
1354
    in_dr = FLD (in_dr);
1355
    out_dr = FLD (out_dr);
1356
    referenced |= 1 << 0;
1357
    referenced |= 1 << 1;
1358
    referenced |= 1 << 2;
1359
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1360
  }
1361
  return cycles;
1362
#undef FLD
1363
}
1364
 
1365
static int
1366
model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
1367
{
1368
#define FLD(f) abuf->fields.sfmt_st_plus.f
1369
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1370
  const IDESC * UNUSED idesc = abuf->idesc;
1371
  int cycles = 0;
1372
  {
1373
    int referenced = 0;
1374
    int UNUSED insn_referenced = abuf->written;
1375
    INT in_src1 = -1;
1376
    INT in_src2 = -1;
1377
    in_src1 = FLD (in_src1);
1378
    in_src2 = FLD (in_src2);
1379
    referenced |= 1 << 0;
1380
    referenced |= 1 << 1;
1381
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1382
  }
1383
  return cycles;
1384
#undef FLD
1385
}
1386
 
1387
static int
1388
model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
1389
{
1390
#define FLD(f) abuf->fields.sfmt_st_plus.f
1391
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1392
  const IDESC * UNUSED idesc = abuf->idesc;
1393
  int cycles = 0;
1394
  {
1395
    int referenced = 0;
1396
    int UNUSED insn_referenced = abuf->written;
1397
    INT in_src1 = -1;
1398
    INT in_src2 = -1;
1399
    in_src1 = FLD (in_src1);
1400
    in_src2 = FLD (in_src2);
1401
    referenced |= 1 << 0;
1402
    referenced |= 1 << 1;
1403
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1404
  }
1405
  return cycles;
1406
#undef FLD
1407
}
1408
 
1409
static int
1410
model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
1411
{
1412
#define FLD(f) abuf->fields.sfmt_st_plus.f
1413
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414
  const IDESC * UNUSED idesc = abuf->idesc;
1415
  int cycles = 0;
1416
  {
1417
    int referenced = 0;
1418
    int UNUSED insn_referenced = abuf->written;
1419
    INT in_src1 = -1;
1420
    INT in_src2 = -1;
1421
    in_src1 = FLD (in_src1);
1422
    in_src2 = FLD (in_src2);
1423
    referenced |= 1 << 0;
1424
    referenced |= 1 << 1;
1425
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1426
  }
1427
  return cycles;
1428
#undef FLD
1429
}
1430
 
1431
static int
1432
model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
1433
{
1434
#define FLD(f) abuf->fields.sfmt_st_plus.f
1435
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436
  const IDESC * UNUSED idesc = abuf->idesc;
1437
  int cycles = 0;
1438
  {
1439
    int referenced = 0;
1440
    int UNUSED insn_referenced = abuf->written;
1441
    INT in_src1 = -1;
1442
    INT in_src2 = -1;
1443
    in_src1 = FLD (in_src1);
1444
    in_src2 = FLD (in_src2);
1445
    referenced |= 1 << 0;
1446
    referenced |= 1 << 1;
1447
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1448
  }
1449
  return cycles;
1450
#undef FLD
1451
}
1452
 
1453
static int
1454
model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
1455
{
1456
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1457
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1458
  const IDESC * UNUSED idesc = abuf->idesc;
1459
  int cycles = 0;
1460
  {
1461
    int referenced = 0;
1462
    int UNUSED insn_referenced = abuf->written;
1463
    INT in_sr = -1;
1464
    INT in_dr = -1;
1465
    INT out_dr = -1;
1466
    in_sr = FLD (in_sr);
1467
    out_dr = FLD (out_dr);
1468
    referenced |= 1 << 0;
1469
    referenced |= 1 << 2;
1470
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1471
  }
1472
  return cycles;
1473
#undef FLD
1474
}
1475
 
1476
static int
1477
model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
1478
{
1479
#define FLD(f) abuf->fields.sfmt_seth.f
1480
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1481
  const IDESC * UNUSED idesc = abuf->idesc;
1482
  int cycles = 0;
1483
  {
1484
    int referenced = 0;
1485
    int UNUSED insn_referenced = abuf->written;
1486
    INT in_sr = -1;
1487
    INT in_dr = -1;
1488
    INT out_dr = -1;
1489
    out_dr = FLD (out_dr);
1490
    referenced |= 1 << 2;
1491
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1492
  }
1493
  return cycles;
1494
#undef FLD
1495
}
1496
 
1497
static int
1498
model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
1499
{
1500
#define FLD(f) abuf->fields.sfmt_seth.f
1501
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502
  const IDESC * UNUSED idesc = abuf->idesc;
1503
  int cycles = 0;
1504
  {
1505
    int referenced = 0;
1506
    int UNUSED insn_referenced = abuf->written;
1507
    INT in_sr = -1;
1508
    INT in_dr = -1;
1509
    INT out_dr = -1;
1510
    out_dr = FLD (out_dr);
1511
    referenced |= 1 << 2;
1512
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1513
  }
1514
  return cycles;
1515
#undef FLD
1516
}
1517
 
1518
static int
1519
model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
1520
{
1521
#define FLD(f) abuf->fields.sfmt_seth.f
1522
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1523
  const IDESC * UNUSED idesc = abuf->idesc;
1524
  int cycles = 0;
1525
  {
1526
    int referenced = 0;
1527
    int UNUSED insn_referenced = abuf->written;
1528
    INT in_sr = -1;
1529
    INT in_dr = -1;
1530
    INT out_dr = -1;
1531
    out_dr = FLD (out_dr);
1532
    referenced |= 1 << 2;
1533
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1534
  }
1535
  return cycles;
1536
#undef FLD
1537
}
1538
 
1539
static int
1540
model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1541
{
1542
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1543
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1544
  const IDESC * UNUSED idesc = abuf->idesc;
1545
  int cycles = 0;
1546
  {
1547
    int referenced = 0;
1548
    int UNUSED insn_referenced = abuf->written;
1549
    INT in_sr = -1;
1550
    INT in_dr = -1;
1551
    INT out_dr = -1;
1552
    out_dr = FLD (out_dr);
1553
    referenced |= 1 << 2;
1554
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1555
  }
1556
  return cycles;
1557
#undef FLD
1558
}
1559
 
1560
static int
1561
model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
1562
{
1563
#define FLD(f) abuf->fields.sfmt_st_plus.f
1564
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1565
  const IDESC * UNUSED idesc = abuf->idesc;
1566
  int cycles = 0;
1567
  {
1568
    int referenced = 0;
1569
    int UNUSED insn_referenced = abuf->written;
1570
    INT in_sr = -1;
1571
    INT in_dr = -1;
1572
    INT out_dr = -1;
1573
    in_sr = FLD (in_src1);
1574
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1575
  }
1576
  return cycles;
1577
#undef FLD
1578
}
1579
 
1580
static int
1581
model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
1582
{
1583
#define FLD(f) abuf->fields.sfmt_st_plus.f
1584
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1585
  const IDESC * UNUSED idesc = abuf->idesc;
1586
  int cycles = 0;
1587
  {
1588
    int referenced = 0;
1589
    int UNUSED insn_referenced = abuf->written;
1590
    INT in_sr = -1;
1591
    INT in_dr = -1;
1592
    INT out_dr = -1;
1593
    in_sr = FLD (in_src1);
1594
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1595
  }
1596
  return cycles;
1597
#undef FLD
1598
}
1599
 
1600
static int
1601
model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1602
{
1603
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1604
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1605
  const IDESC * UNUSED idesc = abuf->idesc;
1606
  int cycles = 0;
1607
  {
1608
    int referenced = 0;
1609
    int UNUSED insn_referenced = abuf->written;
1610
    INT in_sr = -1;
1611
    INT in_dr = -1;
1612
    INT out_dr = -1;
1613
    in_sr = FLD (in_sr);
1614
    referenced |= 1 << 0;
1615
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1616
  }
1617
  return cycles;
1618
#undef FLD
1619
}
1620
 
1621
static int
1622
model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
1623
{
1624
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1625
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1626
  const IDESC * UNUSED idesc = abuf->idesc;
1627
  int cycles = 0;
1628
  {
1629
    int referenced = 0;
1630
    int UNUSED insn_referenced = abuf->written;
1631
    INT in_sr = -1;
1632
    INT in_dr = -1;
1633
    INT out_dr = -1;
1634
    in_sr = FLD (in_sr);
1635
    out_dr = FLD (out_dr);
1636
    referenced |= 1 << 0;
1637
    referenced |= 1 << 2;
1638
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1639
  }
1640
  return cycles;
1641
#undef FLD
1642
}
1643
 
1644
static int
1645
model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
1646
{
1647
#define FLD(f) abuf->fields.sfmt_empty.f
1648
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1649
  const IDESC * UNUSED idesc = abuf->idesc;
1650
  int cycles = 0;
1651
  {
1652
    int referenced = 0;
1653
    int UNUSED insn_referenced = abuf->written;
1654
    INT in_sr = -1;
1655
    INT in_dr = -1;
1656
    INT out_dr = -1;
1657
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1658
  }
1659
  return cycles;
1660
#undef FLD
1661
}
1662
 
1663
static int
1664
model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
1665
{
1666
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1667
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1668
  const IDESC * UNUSED idesc = abuf->idesc;
1669
  int cycles = 0;
1670
  {
1671
    int referenced = 0;
1672
    int UNUSED insn_referenced = abuf->written;
1673
    INT in_sr = -1;
1674
    INT in_dr = -1;
1675
    INT out_dr = -1;
1676
    in_sr = FLD (in_sr);
1677
    out_dr = FLD (out_dr);
1678
    referenced |= 1 << 0;
1679
    referenced |= 1 << 2;
1680
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1681
  }
1682
  return cycles;
1683
#undef FLD
1684
}
1685
 
1686
static int
1687
model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
1688
{
1689
#define FLD(f) abuf->fields.sfmt_empty.f
1690
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1691
  const IDESC * UNUSED idesc = abuf->idesc;
1692
  int cycles = 0;
1693
  {
1694
    int referenced = 0;
1695
    int UNUSED insn_referenced = abuf->written;
1696
    INT in_src1 = -1;
1697
    INT in_src2 = -1;
1698
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1699
  }
1700
  return cycles;
1701
#undef FLD
1702
}
1703
 
1704
static int
1705
model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
1706
{
1707
#define FLD(f) abuf->fields.sfmt_empty.f
1708
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1709
  const IDESC * UNUSED idesc = abuf->idesc;
1710
  int cycles = 0;
1711
  {
1712
    int referenced = 0;
1713
    int UNUSED insn_referenced = abuf->written;
1714
    INT in_src1 = -1;
1715
    INT in_src2 = -1;
1716
    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1717
  }
1718
  return cycles;
1719
#undef FLD
1720
}
1721
 
1722
static int
1723
model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
1724
{
1725
#define FLD(f) abuf->fields.sfmt_empty.f
1726
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1727
  const IDESC * UNUSED idesc = abuf->idesc;
1728
  int cycles = 0;
1729
  {
1730
    int referenced = 0;
1731
    int UNUSED insn_referenced = abuf->written;
1732
    INT in_sr = -1;
1733
    INT in_dr = -1;
1734
    INT out_dr = -1;
1735
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1736
  }
1737
  return cycles;
1738
#undef FLD
1739
}
1740
 
1741
static int
1742
model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
1743
{
1744
#define FLD(f) abuf->fields.sfmt_seth.f
1745
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1746
  const IDESC * UNUSED idesc = abuf->idesc;
1747
  int cycles = 0;
1748
  {
1749
    int referenced = 0;
1750
    int UNUSED insn_referenced = abuf->written;
1751
    INT in_sr = -1;
1752
    INT in_dr = -1;
1753
    INT out_dr = -1;
1754
    out_dr = FLD (out_dr);
1755
    referenced |= 1 << 2;
1756
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1757
  }
1758
  return cycles;
1759
#undef FLD
1760
}
1761
 
1762
static int
1763
model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
1764
{
1765
#define FLD(f) abuf->fields.sfmt_add.f
1766
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1767
  const IDESC * UNUSED idesc = abuf->idesc;
1768
  int cycles = 0;
1769
  {
1770
    int referenced = 0;
1771
    int UNUSED insn_referenced = abuf->written;
1772
    INT in_sr = -1;
1773
    INT in_dr = -1;
1774
    INT out_dr = -1;
1775
    in_sr = FLD (in_sr);
1776
    in_dr = FLD (in_dr);
1777
    out_dr = FLD (out_dr);
1778
    referenced |= 1 << 0;
1779
    referenced |= 1 << 1;
1780
    referenced |= 1 << 2;
1781
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1782
  }
1783
  return cycles;
1784
#undef FLD
1785
}
1786
 
1787
static int
1788
model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1789
{
1790
#define FLD(f) abuf->fields.sfmt_add3.f
1791
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1792
  const IDESC * UNUSED idesc = abuf->idesc;
1793
  int cycles = 0;
1794
  {
1795
    int referenced = 0;
1796
    int UNUSED insn_referenced = abuf->written;
1797
    INT in_sr = -1;
1798
    INT in_dr = -1;
1799
    INT out_dr = -1;
1800
    in_sr = FLD (in_sr);
1801
    out_dr = FLD (out_dr);
1802
    referenced |= 1 << 0;
1803
    referenced |= 1 << 2;
1804
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1805
  }
1806
  return cycles;
1807
#undef FLD
1808
}
1809
 
1810
static int
1811
model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
1812
{
1813
#define FLD(f) abuf->fields.sfmt_slli.f
1814
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1815
  const IDESC * UNUSED idesc = abuf->idesc;
1816
  int cycles = 0;
1817
  {
1818
    int referenced = 0;
1819
    int UNUSED insn_referenced = abuf->written;
1820
    INT in_sr = -1;
1821
    INT in_dr = -1;
1822
    INT out_dr = -1;
1823
    in_dr = FLD (in_dr);
1824
    out_dr = FLD (out_dr);
1825
    referenced |= 1 << 1;
1826
    referenced |= 1 << 2;
1827
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1828
  }
1829
  return cycles;
1830
#undef FLD
1831
}
1832
 
1833
static int
1834
model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
1835
{
1836
#define FLD(f) abuf->fields.sfmt_add.f
1837
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1838
  const IDESC * UNUSED idesc = abuf->idesc;
1839
  int cycles = 0;
1840
  {
1841
    int referenced = 0;
1842
    int UNUSED insn_referenced = abuf->written;
1843
    INT in_sr = -1;
1844
    INT in_dr = -1;
1845
    INT out_dr = -1;
1846
    in_sr = FLD (in_sr);
1847
    in_dr = FLD (in_dr);
1848
    out_dr = FLD (out_dr);
1849
    referenced |= 1 << 0;
1850
    referenced |= 1 << 1;
1851
    referenced |= 1 << 2;
1852
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1853
  }
1854
  return cycles;
1855
#undef FLD
1856
}
1857
 
1858
static int
1859
model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
1860
{
1861
#define FLD(f) abuf->fields.sfmt_add3.f
1862
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1863
  const IDESC * UNUSED idesc = abuf->idesc;
1864
  int cycles = 0;
1865
  {
1866
    int referenced = 0;
1867
    int UNUSED insn_referenced = abuf->written;
1868
    INT in_sr = -1;
1869
    INT in_dr = -1;
1870
    INT out_dr = -1;
1871
    in_sr = FLD (in_sr);
1872
    out_dr = FLD (out_dr);
1873
    referenced |= 1 << 0;
1874
    referenced |= 1 << 2;
1875
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1876
  }
1877
  return cycles;
1878
#undef FLD
1879
}
1880
 
1881
static int
1882
model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
1883
{
1884
#define FLD(f) abuf->fields.sfmt_slli.f
1885
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1886
  const IDESC * UNUSED idesc = abuf->idesc;
1887
  int cycles = 0;
1888
  {
1889
    int referenced = 0;
1890
    int UNUSED insn_referenced = abuf->written;
1891
    INT in_sr = -1;
1892
    INT in_dr = -1;
1893
    INT out_dr = -1;
1894
    in_dr = FLD (in_dr);
1895
    out_dr = FLD (out_dr);
1896
    referenced |= 1 << 1;
1897
    referenced |= 1 << 2;
1898
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1899
  }
1900
  return cycles;
1901
#undef FLD
1902
}
1903
 
1904
static int
1905
model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
1906
{
1907
#define FLD(f) abuf->fields.sfmt_add.f
1908
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1909
  const IDESC * UNUSED idesc = abuf->idesc;
1910
  int cycles = 0;
1911
  {
1912
    int referenced = 0;
1913
    int UNUSED insn_referenced = abuf->written;
1914
    INT in_sr = -1;
1915
    INT in_dr = -1;
1916
    INT out_dr = -1;
1917
    in_sr = FLD (in_sr);
1918
    in_dr = FLD (in_dr);
1919
    out_dr = FLD (out_dr);
1920
    referenced |= 1 << 0;
1921
    referenced |= 1 << 1;
1922
    referenced |= 1 << 2;
1923
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1924
  }
1925
  return cycles;
1926
#undef FLD
1927
}
1928
 
1929
static int
1930
model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
1931
{
1932
#define FLD(f) abuf->fields.sfmt_add3.f
1933
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1934
  const IDESC * UNUSED idesc = abuf->idesc;
1935
  int cycles = 0;
1936
  {
1937
    int referenced = 0;
1938
    int UNUSED insn_referenced = abuf->written;
1939
    INT in_sr = -1;
1940
    INT in_dr = -1;
1941
    INT out_dr = -1;
1942
    in_sr = FLD (in_sr);
1943
    out_dr = FLD (out_dr);
1944
    referenced |= 1 << 0;
1945
    referenced |= 1 << 2;
1946
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1947
  }
1948
  return cycles;
1949
#undef FLD
1950
}
1951
 
1952
static int
1953
model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
1954
{
1955
#define FLD(f) abuf->fields.sfmt_slli.f
1956
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1957
  const IDESC * UNUSED idesc = abuf->idesc;
1958
  int cycles = 0;
1959
  {
1960
    int referenced = 0;
1961
    int UNUSED insn_referenced = abuf->written;
1962
    INT in_sr = -1;
1963
    INT in_dr = -1;
1964
    INT out_dr = -1;
1965
    in_dr = FLD (in_dr);
1966
    out_dr = FLD (out_dr);
1967
    referenced |= 1 << 1;
1968
    referenced |= 1 << 2;
1969
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1970
  }
1971
  return cycles;
1972
#undef FLD
1973
}
1974
 
1975
static int
1976
model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
1977
{
1978
#define FLD(f) abuf->fields.sfmt_st_plus.f
1979
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1980
  const IDESC * UNUSED idesc = abuf->idesc;
1981
  int cycles = 0;
1982
  {
1983
    int referenced = 0;
1984
    int UNUSED insn_referenced = abuf->written;
1985
    INT in_src1 = 0;
1986
    INT in_src2 = 0;
1987
    in_src1 = FLD (in_src1);
1988
    in_src2 = FLD (in_src2);
1989
    referenced |= 1 << 0;
1990
    referenced |= 1 << 1;
1991
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1992
  }
1993
  return cycles;
1994
#undef FLD
1995
}
1996
 
1997
static int
1998
model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
1999
{
2000
#define FLD(f) abuf->fields.sfmt_st_d.f
2001
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2002
  const IDESC * UNUSED idesc = abuf->idesc;
2003
  int cycles = 0;
2004
  {
2005
    int referenced = 0;
2006
    int UNUSED insn_referenced = abuf->written;
2007
    INT in_src1 = 0;
2008
    INT in_src2 = 0;
2009
    in_src1 = FLD (in_src1);
2010
    in_src2 = FLD (in_src2);
2011
    referenced |= 1 << 0;
2012
    referenced |= 1 << 1;
2013
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2014
  }
2015
  return cycles;
2016
#undef FLD
2017
}
2018
 
2019
static int
2020
model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
2021
{
2022
#define FLD(f) abuf->fields.sfmt_st_plus.f
2023
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2024
  const IDESC * UNUSED idesc = abuf->idesc;
2025
  int cycles = 0;
2026
  {
2027
    int referenced = 0;
2028
    int UNUSED insn_referenced = abuf->written;
2029
    INT in_src1 = 0;
2030
    INT in_src2 = 0;
2031
    in_src1 = FLD (in_src1);
2032
    in_src2 = FLD (in_src2);
2033
    referenced |= 1 << 0;
2034
    referenced |= 1 << 1;
2035
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2036
  }
2037
  return cycles;
2038
#undef FLD
2039
}
2040
 
2041
static int
2042
model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2043
{
2044
#define FLD(f) abuf->fields.sfmt_st_d.f
2045
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2046
  const IDESC * UNUSED idesc = abuf->idesc;
2047
  int cycles = 0;
2048
  {
2049
    int referenced = 0;
2050
    int UNUSED insn_referenced = abuf->written;
2051
    INT in_src1 = 0;
2052
    INT in_src2 = 0;
2053
    in_src1 = FLD (in_src1);
2054
    in_src2 = FLD (in_src2);
2055
    referenced |= 1 << 0;
2056
    referenced |= 1 << 1;
2057
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2058
  }
2059
  return cycles;
2060
#undef FLD
2061
}
2062
 
2063
static int
2064
model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
2065
{
2066
#define FLD(f) abuf->fields.sfmt_st_plus.f
2067
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2068
  const IDESC * UNUSED idesc = abuf->idesc;
2069
  int cycles = 0;
2070
  {
2071
    int referenced = 0;
2072
    int UNUSED insn_referenced = abuf->written;
2073
    INT in_src1 = 0;
2074
    INT in_src2 = 0;
2075
    in_src1 = FLD (in_src1);
2076
    in_src2 = FLD (in_src2);
2077
    referenced |= 1 << 0;
2078
    referenced |= 1 << 1;
2079
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2080
  }
2081
  return cycles;
2082
#undef FLD
2083
}
2084
 
2085
static int
2086
model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2087
{
2088
#define FLD(f) abuf->fields.sfmt_st_d.f
2089
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2090
  const IDESC * UNUSED idesc = abuf->idesc;
2091
  int cycles = 0;
2092
  {
2093
    int referenced = 0;
2094
    int UNUSED insn_referenced = abuf->written;
2095
    INT in_src1 = 0;
2096
    INT in_src2 = 0;
2097
    in_src1 = FLD (in_src1);
2098
    in_src2 = FLD (in_src2);
2099
    referenced |= 1 << 0;
2100
    referenced |= 1 << 1;
2101
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2102
  }
2103
  return cycles;
2104
#undef FLD
2105
}
2106
 
2107
static int
2108
model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2109
{
2110
#define FLD(f) abuf->fields.sfmt_st_plus.f
2111
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2112
  const IDESC * UNUSED idesc = abuf->idesc;
2113
  int cycles = 0;
2114
  {
2115
    int referenced = 0;
2116
    int UNUSED insn_referenced = abuf->written;
2117
    INT in_src1 = 0;
2118
    INT in_src2 = 0;
2119
    in_src1 = FLD (in_src1);
2120
    in_src2 = FLD (in_src2);
2121
    referenced |= 1 << 0;
2122
    referenced |= 1 << 1;
2123
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2124
  }
2125
  {
2126
    int referenced = 0;
2127
    int UNUSED insn_referenced = abuf->written;
2128
    INT in_sr = -1;
2129
    INT in_dr = -1;
2130
    INT out_dr = -1;
2131
    in_dr = FLD (in_src2);
2132
    out_dr = FLD (out_src2);
2133
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2134
  }
2135
  return cycles;
2136
#undef FLD
2137
}
2138
 
2139
static int
2140
model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2141
{
2142
#define FLD(f) abuf->fields.sfmt_st_plus.f
2143
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2144
  const IDESC * UNUSED idesc = abuf->idesc;
2145
  int cycles = 0;
2146
  {
2147
    int referenced = 0;
2148
    int UNUSED insn_referenced = abuf->written;
2149
    INT in_src1 = 0;
2150
    INT in_src2 = 0;
2151
    in_src1 = FLD (in_src1);
2152
    in_src2 = FLD (in_src2);
2153
    referenced |= 1 << 0;
2154
    referenced |= 1 << 1;
2155
    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2156
  }
2157
  {
2158
    int referenced = 0;
2159
    int UNUSED insn_referenced = abuf->written;
2160
    INT in_sr = -1;
2161
    INT in_dr = -1;
2162
    INT out_dr = -1;
2163
    in_dr = FLD (in_src2);
2164
    out_dr = FLD (out_src2);
2165
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2166
  }
2167
  return cycles;
2168
#undef FLD
2169
}
2170
 
2171
static int
2172
model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
2173
{
2174
#define FLD(f) abuf->fields.sfmt_add.f
2175
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2176
  const IDESC * UNUSED idesc = abuf->idesc;
2177
  int cycles = 0;
2178
  {
2179
    int referenced = 0;
2180
    int UNUSED insn_referenced = abuf->written;
2181
    INT in_sr = -1;
2182
    INT in_dr = -1;
2183
    INT out_dr = -1;
2184
    in_sr = FLD (in_sr);
2185
    in_dr = FLD (in_dr);
2186
    out_dr = FLD (out_dr);
2187
    referenced |= 1 << 0;
2188
    referenced |= 1 << 1;
2189
    referenced |= 1 << 2;
2190
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2191
  }
2192
  return cycles;
2193
#undef FLD
2194
}
2195
 
2196
static int
2197
model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
2198
{
2199
#define FLD(f) abuf->fields.sfmt_add.f
2200
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2201
  const IDESC * UNUSED idesc = abuf->idesc;
2202
  int cycles = 0;
2203
  {
2204
    int referenced = 0;
2205
    int UNUSED insn_referenced = abuf->written;
2206
    INT in_sr = -1;
2207
    INT in_dr = -1;
2208
    INT out_dr = -1;
2209
    in_sr = FLD (in_sr);
2210
    in_dr = FLD (in_dr);
2211
    out_dr = FLD (out_dr);
2212
    referenced |= 1 << 0;
2213
    referenced |= 1 << 1;
2214
    referenced |= 1 << 2;
2215
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2216
  }
2217
  return cycles;
2218
#undef FLD
2219
}
2220
 
2221
static int
2222
model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
2223
{
2224
#define FLD(f) abuf->fields.sfmt_add.f
2225
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2226
  const IDESC * UNUSED idesc = abuf->idesc;
2227
  int cycles = 0;
2228
  {
2229
    int referenced = 0;
2230
    int UNUSED insn_referenced = abuf->written;
2231
    INT in_sr = -1;
2232
    INT in_dr = -1;
2233
    INT out_dr = -1;
2234
    in_sr = FLD (in_sr);
2235
    in_dr = FLD (in_dr);
2236
    out_dr = FLD (out_dr);
2237
    referenced |= 1 << 0;
2238
    referenced |= 1 << 1;
2239
    referenced |= 1 << 2;
2240
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2241
  }
2242
  return cycles;
2243
#undef FLD
2244
}
2245
 
2246
static int
2247
model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
2248
{
2249
#define FLD(f) abuf->fields.sfmt_trap.f
2250
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2251
  const IDESC * UNUSED idesc = abuf->idesc;
2252
  int cycles = 0;
2253
  {
2254
    int referenced = 0;
2255
    int UNUSED insn_referenced = abuf->written;
2256
    INT in_sr = -1;
2257
    INT in_dr = -1;
2258
    INT out_dr = -1;
2259
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2260
  }
2261
  return cycles;
2262
#undef FLD
2263
}
2264
 
2265
static int
2266
model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
2267
{
2268
#define FLD(f) abuf->fields.sfmt_st_plus.f
2269
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2270
  const IDESC * UNUSED idesc = abuf->idesc;
2271
  int cycles = 0;
2272
  {
2273
    int referenced = 0;
2274
    int UNUSED insn_referenced = abuf->written;
2275
    INT in_sr = 0;
2276
    INT out_dr = 0;
2277
    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
2278
  }
2279
  return cycles;
2280
#undef FLD
2281
}
2282
 
2283
static int
2284
model_m32r_d_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
2285
{
2286
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2287
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2288
  const IDESC * UNUSED idesc = abuf->idesc;
2289
  int cycles = 0;
2290
  {
2291
    int referenced = 0;
2292
    int UNUSED insn_referenced = abuf->written;
2293
    INT in_sr = -1;
2294
    INT in_dr = -1;
2295
    INT out_dr = -1;
2296
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2297
  }
2298
  return cycles;
2299
#undef FLD
2300
}
2301
 
2302
static int
2303
model_m32r_d_setpsw (SIM_CPU *current_cpu, void *sem_arg)
2304
{
2305
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2306
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2307
  const IDESC * UNUSED idesc = abuf->idesc;
2308
  int cycles = 0;
2309
  {
2310
    int referenced = 0;
2311
    int UNUSED insn_referenced = abuf->written;
2312
    INT in_sr = -1;
2313
    INT in_dr = -1;
2314
    INT out_dr = -1;
2315
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2316
  }
2317
  return cycles;
2318
#undef FLD
2319
}
2320
 
2321
static int
2322
model_m32r_d_bset (SIM_CPU *current_cpu, void *sem_arg)
2323
{
2324
#define FLD(f) abuf->fields.sfmt_bset.f
2325
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2326
  const IDESC * UNUSED idesc = abuf->idesc;
2327
  int cycles = 0;
2328
  {
2329
    int referenced = 0;
2330
    int UNUSED insn_referenced = abuf->written;
2331
    INT in_sr = -1;
2332
    INT in_dr = -1;
2333
    INT out_dr = -1;
2334
    in_sr = FLD (in_sr);
2335
    referenced |= 1 << 0;
2336
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2337
  }
2338
  return cycles;
2339
#undef FLD
2340
}
2341
 
2342
static int
2343
model_m32r_d_bclr (SIM_CPU *current_cpu, void *sem_arg)
2344
{
2345
#define FLD(f) abuf->fields.sfmt_bset.f
2346
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2347
  const IDESC * UNUSED idesc = abuf->idesc;
2348
  int cycles = 0;
2349
  {
2350
    int referenced = 0;
2351
    int UNUSED insn_referenced = abuf->written;
2352
    INT in_sr = -1;
2353
    INT in_dr = -1;
2354
    INT out_dr = -1;
2355
    in_sr = FLD (in_sr);
2356
    referenced |= 1 << 0;
2357
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2358
  }
2359
  return cycles;
2360
#undef FLD
2361
}
2362
 
2363
static int
2364
model_m32r_d_btst (SIM_CPU *current_cpu, void *sem_arg)
2365
{
2366
#define FLD(f) abuf->fields.sfmt_bset.f
2367
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2368
  const IDESC * UNUSED idesc = abuf->idesc;
2369
  int cycles = 0;
2370
  {
2371
    int referenced = 0;
2372
    int UNUSED insn_referenced = abuf->written;
2373
    INT in_sr = -1;
2374
    INT in_dr = -1;
2375
    INT out_dr = -1;
2376
    in_sr = FLD (in_sr);
2377
    referenced |= 1 << 0;
2378
    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2379
  }
2380
  return cycles;
2381
#undef FLD
2382
}
2383
 
2384
static int
2385
model_test_add (SIM_CPU *current_cpu, void *sem_arg)
2386
{
2387
#define FLD(f) abuf->fields.sfmt_add.f
2388
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2389
  const IDESC * UNUSED idesc = abuf->idesc;
2390
  int cycles = 0;
2391
  {
2392
    int referenced = 0;
2393
    int UNUSED insn_referenced = abuf->written;
2394
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2395
  }
2396
  return cycles;
2397
#undef FLD
2398
}
2399
 
2400
static int
2401
model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
2402
{
2403
#define FLD(f) abuf->fields.sfmt_add3.f
2404
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2405
  const IDESC * UNUSED idesc = abuf->idesc;
2406
  int cycles = 0;
2407
  {
2408
    int referenced = 0;
2409
    int UNUSED insn_referenced = abuf->written;
2410
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2411
  }
2412
  return cycles;
2413
#undef FLD
2414
}
2415
 
2416
static int
2417
model_test_and (SIM_CPU *current_cpu, void *sem_arg)
2418
{
2419
#define FLD(f) abuf->fields.sfmt_add.f
2420
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2421
  const IDESC * UNUSED idesc = abuf->idesc;
2422
  int cycles = 0;
2423
  {
2424
    int referenced = 0;
2425
    int UNUSED insn_referenced = abuf->written;
2426
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2427
  }
2428
  return cycles;
2429
#undef FLD
2430
}
2431
 
2432
static int
2433
model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
2434
{
2435
#define FLD(f) abuf->fields.sfmt_and3.f
2436
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2437
  const IDESC * UNUSED idesc = abuf->idesc;
2438
  int cycles = 0;
2439
  {
2440
    int referenced = 0;
2441
    int UNUSED insn_referenced = abuf->written;
2442
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2443
  }
2444
  return cycles;
2445
#undef FLD
2446
}
2447
 
2448
static int
2449
model_test_or (SIM_CPU *current_cpu, void *sem_arg)
2450
{
2451
#define FLD(f) abuf->fields.sfmt_add.f
2452
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2453
  const IDESC * UNUSED idesc = abuf->idesc;
2454
  int cycles = 0;
2455
  {
2456
    int referenced = 0;
2457
    int UNUSED insn_referenced = abuf->written;
2458
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2459
  }
2460
  return cycles;
2461
#undef FLD
2462
}
2463
 
2464
static int
2465
model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
2466
{
2467
#define FLD(f) abuf->fields.sfmt_and3.f
2468
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2469
  const IDESC * UNUSED idesc = abuf->idesc;
2470
  int cycles = 0;
2471
  {
2472
    int referenced = 0;
2473
    int UNUSED insn_referenced = abuf->written;
2474
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2475
  }
2476
  return cycles;
2477
#undef FLD
2478
}
2479
 
2480
static int
2481
model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
2482
{
2483
#define FLD(f) abuf->fields.sfmt_add.f
2484
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2485
  const IDESC * UNUSED idesc = abuf->idesc;
2486
  int cycles = 0;
2487
  {
2488
    int referenced = 0;
2489
    int UNUSED insn_referenced = abuf->written;
2490
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2491
  }
2492
  return cycles;
2493
#undef FLD
2494
}
2495
 
2496
static int
2497
model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
2498
{
2499
#define FLD(f) abuf->fields.sfmt_and3.f
2500
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2501
  const IDESC * UNUSED idesc = abuf->idesc;
2502
  int cycles = 0;
2503
  {
2504
    int referenced = 0;
2505
    int UNUSED insn_referenced = abuf->written;
2506
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2507
  }
2508
  return cycles;
2509
#undef FLD
2510
}
2511
 
2512
static int
2513
model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
2514
{
2515
#define FLD(f) abuf->fields.sfmt_addi.f
2516
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2517
  const IDESC * UNUSED idesc = abuf->idesc;
2518
  int cycles = 0;
2519
  {
2520
    int referenced = 0;
2521
    int UNUSED insn_referenced = abuf->written;
2522
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2523
  }
2524
  return cycles;
2525
#undef FLD
2526
}
2527
 
2528
static int
2529
model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
2530
{
2531
#define FLD(f) abuf->fields.sfmt_add.f
2532
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2533
  const IDESC * UNUSED idesc = abuf->idesc;
2534
  int cycles = 0;
2535
  {
2536
    int referenced = 0;
2537
    int UNUSED insn_referenced = abuf->written;
2538
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2539
  }
2540
  return cycles;
2541
#undef FLD
2542
}
2543
 
2544
static int
2545
model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
2546
{
2547
#define FLD(f) abuf->fields.sfmt_add3.f
2548
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2549
  const IDESC * UNUSED idesc = abuf->idesc;
2550
  int cycles = 0;
2551
  {
2552
    int referenced = 0;
2553
    int UNUSED insn_referenced = abuf->written;
2554
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2555
  }
2556
  return cycles;
2557
#undef FLD
2558
}
2559
 
2560
static int
2561
model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
2562
{
2563
#define FLD(f) abuf->fields.sfmt_add.f
2564
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2565
  const IDESC * UNUSED idesc = abuf->idesc;
2566
  int cycles = 0;
2567
  {
2568
    int referenced = 0;
2569
    int UNUSED insn_referenced = abuf->written;
2570
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2571
  }
2572
  return cycles;
2573
#undef FLD
2574
}
2575
 
2576
static int
2577
model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
2578
{
2579
#define FLD(f) abuf->fields.sfmt_bl8.f
2580
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2581
  const IDESC * UNUSED idesc = abuf->idesc;
2582
  int cycles = 0;
2583
  {
2584
    int referenced = 0;
2585
    int UNUSED insn_referenced = abuf->written;
2586
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2587
  }
2588
  return cycles;
2589
#undef FLD
2590
}
2591
 
2592
static int
2593
model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
2594
{
2595
#define FLD(f) abuf->fields.sfmt_bl24.f
2596
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2597
  const IDESC * UNUSED idesc = abuf->idesc;
2598
  int cycles = 0;
2599
  {
2600
    int referenced = 0;
2601
    int UNUSED insn_referenced = abuf->written;
2602
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2603
  }
2604
  return cycles;
2605
#undef FLD
2606
}
2607
 
2608
static int
2609
model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
2610
{
2611
#define FLD(f) abuf->fields.sfmt_beq.f
2612
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2613
  const IDESC * UNUSED idesc = abuf->idesc;
2614
  int cycles = 0;
2615
  {
2616
    int referenced = 0;
2617
    int UNUSED insn_referenced = abuf->written;
2618
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2619
  }
2620
  return cycles;
2621
#undef FLD
2622
}
2623
 
2624
static int
2625
model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
2626
{
2627
#define FLD(f) abuf->fields.sfmt_beq.f
2628
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2629
  const IDESC * UNUSED idesc = abuf->idesc;
2630
  int cycles = 0;
2631
  {
2632
    int referenced = 0;
2633
    int UNUSED insn_referenced = abuf->written;
2634
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2635
  }
2636
  return cycles;
2637
#undef FLD
2638
}
2639
 
2640
static int
2641
model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
2642
{
2643
#define FLD(f) abuf->fields.sfmt_beq.f
2644
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2645
  const IDESC * UNUSED idesc = abuf->idesc;
2646
  int cycles = 0;
2647
  {
2648
    int referenced = 0;
2649
    int UNUSED insn_referenced = abuf->written;
2650
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2651
  }
2652
  return cycles;
2653
#undef FLD
2654
}
2655
 
2656
static int
2657
model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
2658
{
2659
#define FLD(f) abuf->fields.sfmt_beq.f
2660
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2661
  const IDESC * UNUSED idesc = abuf->idesc;
2662
  int cycles = 0;
2663
  {
2664
    int referenced = 0;
2665
    int UNUSED insn_referenced = abuf->written;
2666
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2667
  }
2668
  return cycles;
2669
#undef FLD
2670
}
2671
 
2672
static int
2673
model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
2674
{
2675
#define FLD(f) abuf->fields.sfmt_beq.f
2676
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2677
  const IDESC * UNUSED idesc = abuf->idesc;
2678
  int cycles = 0;
2679
  {
2680
    int referenced = 0;
2681
    int UNUSED insn_referenced = abuf->written;
2682
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2683
  }
2684
  return cycles;
2685
#undef FLD
2686
}
2687
 
2688
static int
2689
model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
2690
{
2691
#define FLD(f) abuf->fields.sfmt_beq.f
2692
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2693
  const IDESC * UNUSED idesc = abuf->idesc;
2694
  int cycles = 0;
2695
  {
2696
    int referenced = 0;
2697
    int UNUSED insn_referenced = abuf->written;
2698
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2699
  }
2700
  return cycles;
2701
#undef FLD
2702
}
2703
 
2704
static int
2705
model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
2706
{
2707
#define FLD(f) abuf->fields.sfmt_beq.f
2708
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2709
  const IDESC * UNUSED idesc = abuf->idesc;
2710
  int cycles = 0;
2711
  {
2712
    int referenced = 0;
2713
    int UNUSED insn_referenced = abuf->written;
2714
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2715
  }
2716
  return cycles;
2717
#undef FLD
2718
}
2719
 
2720
static int
2721
model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
2722
{
2723
#define FLD(f) abuf->fields.sfmt_bl8.f
2724
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2725
  const IDESC * UNUSED idesc = abuf->idesc;
2726
  int cycles = 0;
2727
  {
2728
    int referenced = 0;
2729
    int UNUSED insn_referenced = abuf->written;
2730
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2731
  }
2732
  return cycles;
2733
#undef FLD
2734
}
2735
 
2736
static int
2737
model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
2738
{
2739
#define FLD(f) abuf->fields.sfmt_bl24.f
2740
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2741
  const IDESC * UNUSED idesc = abuf->idesc;
2742
  int cycles = 0;
2743
  {
2744
    int referenced = 0;
2745
    int UNUSED insn_referenced = abuf->written;
2746
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2747
  }
2748
  return cycles;
2749
#undef FLD
2750
}
2751
 
2752
static int
2753
model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
2754
{
2755
#define FLD(f) abuf->fields.sfmt_bl8.f
2756
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2757
  const IDESC * UNUSED idesc = abuf->idesc;
2758
  int cycles = 0;
2759
  {
2760
    int referenced = 0;
2761
    int UNUSED insn_referenced = abuf->written;
2762
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2763
  }
2764
  return cycles;
2765
#undef FLD
2766
}
2767
 
2768
static int
2769
model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
2770
{
2771
#define FLD(f) abuf->fields.sfmt_bl24.f
2772
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2773
  const IDESC * UNUSED idesc = abuf->idesc;
2774
  int cycles = 0;
2775
  {
2776
    int referenced = 0;
2777
    int UNUSED insn_referenced = abuf->written;
2778
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2779
  }
2780
  return cycles;
2781
#undef FLD
2782
}
2783
 
2784
static int
2785
model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
2786
{
2787
#define FLD(f) abuf->fields.sfmt_beq.f
2788
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2789
  const IDESC * UNUSED idesc = abuf->idesc;
2790
  int cycles = 0;
2791
  {
2792
    int referenced = 0;
2793
    int UNUSED insn_referenced = abuf->written;
2794
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2795
  }
2796
  return cycles;
2797
#undef FLD
2798
}
2799
 
2800
static int
2801
model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
2802
{
2803
#define FLD(f) abuf->fields.sfmt_bl8.f
2804
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2805
  const IDESC * UNUSED idesc = abuf->idesc;
2806
  int cycles = 0;
2807
  {
2808
    int referenced = 0;
2809
    int UNUSED insn_referenced = abuf->written;
2810
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2811
  }
2812
  return cycles;
2813
#undef FLD
2814
}
2815
 
2816
static int
2817
model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
2818
{
2819
#define FLD(f) abuf->fields.sfmt_bl24.f
2820
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2821
  const IDESC * UNUSED idesc = abuf->idesc;
2822
  int cycles = 0;
2823
  {
2824
    int referenced = 0;
2825
    int UNUSED insn_referenced = abuf->written;
2826
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2827
  }
2828
  return cycles;
2829
#undef FLD
2830
}
2831
 
2832
static int
2833
model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
2834
{
2835
#define FLD(f) abuf->fields.sfmt_st_plus.f
2836
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2837
  const IDESC * UNUSED idesc = abuf->idesc;
2838
  int cycles = 0;
2839
  {
2840
    int referenced = 0;
2841
    int UNUSED insn_referenced = abuf->written;
2842
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2843
  }
2844
  return cycles;
2845
#undef FLD
2846
}
2847
 
2848
static int
2849
model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
2850
{
2851
#define FLD(f) abuf->fields.sfmt_st_d.f
2852
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2853
  const IDESC * UNUSED idesc = abuf->idesc;
2854
  int cycles = 0;
2855
  {
2856
    int referenced = 0;
2857
    int UNUSED insn_referenced = abuf->written;
2858
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2859
  }
2860
  return cycles;
2861
#undef FLD
2862
}
2863
 
2864
static int
2865
model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
2866
{
2867
#define FLD(f) abuf->fields.sfmt_st_plus.f
2868
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2869
  const IDESC * UNUSED idesc = abuf->idesc;
2870
  int cycles = 0;
2871
  {
2872
    int referenced = 0;
2873
    int UNUSED insn_referenced = abuf->written;
2874
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2875
  }
2876
  return cycles;
2877
#undef FLD
2878
}
2879
 
2880
static int
2881
model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
2882
{
2883
#define FLD(f) abuf->fields.sfmt_st_d.f
2884
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2885
  const IDESC * UNUSED idesc = abuf->idesc;
2886
  int cycles = 0;
2887
  {
2888
    int referenced = 0;
2889
    int UNUSED insn_referenced = abuf->written;
2890
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2891
  }
2892
  return cycles;
2893
#undef FLD
2894
}
2895
 
2896
static int
2897
model_test_div (SIM_CPU *current_cpu, void *sem_arg)
2898
{
2899
#define FLD(f) abuf->fields.sfmt_add.f
2900
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2901
  const IDESC * UNUSED idesc = abuf->idesc;
2902
  int cycles = 0;
2903
  {
2904
    int referenced = 0;
2905
    int UNUSED insn_referenced = abuf->written;
2906
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2907
  }
2908
  return cycles;
2909
#undef FLD
2910
}
2911
 
2912
static int
2913
model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
2914
{
2915
#define FLD(f) abuf->fields.sfmt_add.f
2916
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2917
  const IDESC * UNUSED idesc = abuf->idesc;
2918
  int cycles = 0;
2919
  {
2920
    int referenced = 0;
2921
    int UNUSED insn_referenced = abuf->written;
2922
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2923
  }
2924
  return cycles;
2925
#undef FLD
2926
}
2927
 
2928
static int
2929
model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
2930
{
2931
#define FLD(f) abuf->fields.sfmt_add.f
2932
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2933
  const IDESC * UNUSED idesc = abuf->idesc;
2934
  int cycles = 0;
2935
  {
2936
    int referenced = 0;
2937
    int UNUSED insn_referenced = abuf->written;
2938
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2939
  }
2940
  return cycles;
2941
#undef FLD
2942
}
2943
 
2944
static int
2945
model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
2946
{
2947
#define FLD(f) abuf->fields.sfmt_add.f
2948
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2949
  const IDESC * UNUSED idesc = abuf->idesc;
2950
  int cycles = 0;
2951
  {
2952
    int referenced = 0;
2953
    int UNUSED insn_referenced = abuf->written;
2954
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2955
  }
2956
  return cycles;
2957
#undef FLD
2958
}
2959
 
2960
static int
2961
model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
2962
{
2963
#define FLD(f) abuf->fields.sfmt_jl.f
2964
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2965
  const IDESC * UNUSED idesc = abuf->idesc;
2966
  int cycles = 0;
2967
  {
2968
    int referenced = 0;
2969
    int UNUSED insn_referenced = abuf->written;
2970
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2971
  }
2972
  return cycles;
2973
#undef FLD
2974
}
2975
 
2976
static int
2977
model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
2978
{
2979
#define FLD(f) abuf->fields.sfmt_jl.f
2980
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2981
  const IDESC * UNUSED idesc = abuf->idesc;
2982
  int cycles = 0;
2983
  {
2984
    int referenced = 0;
2985
    int UNUSED insn_referenced = abuf->written;
2986
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2987
  }
2988
  return cycles;
2989
#undef FLD
2990
}
2991
 
2992
static int
2993
model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
2994
{
2995
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2996
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2997
  const IDESC * UNUSED idesc = abuf->idesc;
2998
  int cycles = 0;
2999
  {
3000
    int referenced = 0;
3001
    int UNUSED insn_referenced = abuf->written;
3002
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3003
  }
3004
  return cycles;
3005
#undef FLD
3006
}
3007
 
3008
static int
3009
model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
3010
{
3011
#define FLD(f) abuf->fields.sfmt_add3.f
3012
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3013
  const IDESC * UNUSED idesc = abuf->idesc;
3014
  int cycles = 0;
3015
  {
3016
    int referenced = 0;
3017
    int UNUSED insn_referenced = abuf->written;
3018
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3019
  }
3020
  return cycles;
3021
#undef FLD
3022
}
3023
 
3024
static int
3025
model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
3026
{
3027
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3028
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3029
  const IDESC * UNUSED idesc = abuf->idesc;
3030
  int cycles = 0;
3031
  {
3032
    int referenced = 0;
3033
    int UNUSED insn_referenced = abuf->written;
3034
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3035
  }
3036
  return cycles;
3037
#undef FLD
3038
}
3039
 
3040
static int
3041
model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
3042
{
3043
#define FLD(f) abuf->fields.sfmt_add3.f
3044
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3045
  const IDESC * UNUSED idesc = abuf->idesc;
3046
  int cycles = 0;
3047
  {
3048
    int referenced = 0;
3049
    int UNUSED insn_referenced = abuf->written;
3050
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3051
  }
3052
  return cycles;
3053
#undef FLD
3054
}
3055
 
3056
static int
3057
model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
3058
{
3059
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3060
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3061
  const IDESC * UNUSED idesc = abuf->idesc;
3062
  int cycles = 0;
3063
  {
3064
    int referenced = 0;
3065
    int UNUSED insn_referenced = abuf->written;
3066
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3067
  }
3068
  return cycles;
3069
#undef FLD
3070
}
3071
 
3072
static int
3073
model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
3074
{
3075
#define FLD(f) abuf->fields.sfmt_add3.f
3076
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3077
  const IDESC * UNUSED idesc = abuf->idesc;
3078
  int cycles = 0;
3079
  {
3080
    int referenced = 0;
3081
    int UNUSED insn_referenced = abuf->written;
3082
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3083
  }
3084
  return cycles;
3085
#undef FLD
3086
}
3087
 
3088
static int
3089
model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
3090
{
3091
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3092
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3093
  const IDESC * UNUSED idesc = abuf->idesc;
3094
  int cycles = 0;
3095
  {
3096
    int referenced = 0;
3097
    int UNUSED insn_referenced = abuf->written;
3098
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3099
  }
3100
  return cycles;
3101
#undef FLD
3102
}
3103
 
3104
static int
3105
model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
3106
{
3107
#define FLD(f) abuf->fields.sfmt_add3.f
3108
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3109
  const IDESC * UNUSED idesc = abuf->idesc;
3110
  int cycles = 0;
3111
  {
3112
    int referenced = 0;
3113
    int UNUSED insn_referenced = abuf->written;
3114
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3115
  }
3116
  return cycles;
3117
#undef FLD
3118
}
3119
 
3120
static int
3121
model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
3122
{
3123
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3124
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3125
  const IDESC * UNUSED idesc = abuf->idesc;
3126
  int cycles = 0;
3127
  {
3128
    int referenced = 0;
3129
    int UNUSED insn_referenced = abuf->written;
3130
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3131
  }
3132
  return cycles;
3133
#undef FLD
3134
}
3135
 
3136
static int
3137
model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
3138
{
3139
#define FLD(f) abuf->fields.sfmt_add3.f
3140
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3141
  const IDESC * UNUSED idesc = abuf->idesc;
3142
  int cycles = 0;
3143
  {
3144
    int referenced = 0;
3145
    int UNUSED insn_referenced = abuf->written;
3146
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3147
  }
3148
  return cycles;
3149
#undef FLD
3150
}
3151
 
3152
static int
3153
model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
3154
{
3155
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3156
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3157
  const IDESC * UNUSED idesc = abuf->idesc;
3158
  int cycles = 0;
3159
  {
3160
    int referenced = 0;
3161
    int UNUSED insn_referenced = abuf->written;
3162
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3163
  }
3164
  return cycles;
3165
#undef FLD
3166
}
3167
 
3168
static int
3169
model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
3170
{
3171
#define FLD(f) abuf->fields.sfmt_ld24.f
3172
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3173
  const IDESC * UNUSED idesc = abuf->idesc;
3174
  int cycles = 0;
3175
  {
3176
    int referenced = 0;
3177
    int UNUSED insn_referenced = abuf->written;
3178
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3179
  }
3180
  return cycles;
3181
#undef FLD
3182
}
3183
 
3184
static int
3185
model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
3186
{
3187
#define FLD(f) abuf->fields.sfmt_addi.f
3188
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3189
  const IDESC * UNUSED idesc = abuf->idesc;
3190
  int cycles = 0;
3191
  {
3192
    int referenced = 0;
3193
    int UNUSED insn_referenced = abuf->written;
3194
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3195
  }
3196
  return cycles;
3197
#undef FLD
3198
}
3199
 
3200
static int
3201
model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
3202
{
3203
#define FLD(f) abuf->fields.sfmt_add3.f
3204
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3205
  const IDESC * UNUSED idesc = abuf->idesc;
3206
  int cycles = 0;
3207
  {
3208
    int referenced = 0;
3209
    int UNUSED insn_referenced = abuf->written;
3210
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3211
  }
3212
  return cycles;
3213
#undef FLD
3214
}
3215
 
3216
static int
3217
model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
3218
{
3219
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3220
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3221
  const IDESC * UNUSED idesc = abuf->idesc;
3222
  int cycles = 0;
3223
  {
3224
    int referenced = 0;
3225
    int UNUSED insn_referenced = abuf->written;
3226
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3227
  }
3228
  return cycles;
3229
#undef FLD
3230
}
3231
 
3232
static int
3233
model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
3234
{
3235
#define FLD(f) abuf->fields.sfmt_st_plus.f
3236
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3237
  const IDESC * UNUSED idesc = abuf->idesc;
3238
  int cycles = 0;
3239
  {
3240
    int referenced = 0;
3241
    int UNUSED insn_referenced = abuf->written;
3242
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3243
  }
3244
  return cycles;
3245
#undef FLD
3246
}
3247
 
3248
static int
3249
model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
3250
{
3251
#define FLD(f) abuf->fields.sfmt_st_plus.f
3252
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3253
  const IDESC * UNUSED idesc = abuf->idesc;
3254
  int cycles = 0;
3255
  {
3256
    int referenced = 0;
3257
    int UNUSED insn_referenced = abuf->written;
3258
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3259
  }
3260
  return cycles;
3261
#undef FLD
3262
}
3263
 
3264
static int
3265
model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
3266
{
3267
#define FLD(f) abuf->fields.sfmt_st_plus.f
3268
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3269
  const IDESC * UNUSED idesc = abuf->idesc;
3270
  int cycles = 0;
3271
  {
3272
    int referenced = 0;
3273
    int UNUSED insn_referenced = abuf->written;
3274
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3275
  }
3276
  return cycles;
3277
#undef FLD
3278
}
3279
 
3280
static int
3281
model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
3282
{
3283
#define FLD(f) abuf->fields.sfmt_st_plus.f
3284
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3285
  const IDESC * UNUSED idesc = abuf->idesc;
3286
  int cycles = 0;
3287
  {
3288
    int referenced = 0;
3289
    int UNUSED insn_referenced = abuf->written;
3290
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3291
  }
3292
  return cycles;
3293
#undef FLD
3294
}
3295
 
3296
static int
3297
model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
3298
{
3299
#define FLD(f) abuf->fields.sfmt_add.f
3300
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3301
  const IDESC * UNUSED idesc = abuf->idesc;
3302
  int cycles = 0;
3303
  {
3304
    int referenced = 0;
3305
    int UNUSED insn_referenced = abuf->written;
3306
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3307
  }
3308
  return cycles;
3309
#undef FLD
3310
}
3311
 
3312
static int
3313
model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
3314
{
3315
#define FLD(f) abuf->fields.sfmt_st_plus.f
3316
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3317
  const IDESC * UNUSED idesc = abuf->idesc;
3318
  int cycles = 0;
3319
  {
3320
    int referenced = 0;
3321
    int UNUSED insn_referenced = abuf->written;
3322
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3323
  }
3324
  return cycles;
3325
#undef FLD
3326
}
3327
 
3328
static int
3329
model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
3330
{
3331
#define FLD(f) abuf->fields.sfmt_st_plus.f
3332
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3333
  const IDESC * UNUSED idesc = abuf->idesc;
3334
  int cycles = 0;
3335
  {
3336
    int referenced = 0;
3337
    int UNUSED insn_referenced = abuf->written;
3338
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3339
  }
3340
  return cycles;
3341
#undef FLD
3342
}
3343
 
3344
static int
3345
model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
3346
{
3347
#define FLD(f) abuf->fields.sfmt_st_plus.f
3348
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3349
  const IDESC * UNUSED idesc = abuf->idesc;
3350
  int cycles = 0;
3351
  {
3352
    int referenced = 0;
3353
    int UNUSED insn_referenced = abuf->written;
3354
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3355
  }
3356
  return cycles;
3357
#undef FLD
3358
}
3359
 
3360
static int
3361
model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
3362
{
3363
#define FLD(f) abuf->fields.sfmt_st_plus.f
3364
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3365
  const IDESC * UNUSED idesc = abuf->idesc;
3366
  int cycles = 0;
3367
  {
3368
    int referenced = 0;
3369
    int UNUSED insn_referenced = abuf->written;
3370
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3371
  }
3372
  return cycles;
3373
#undef FLD
3374
}
3375
 
3376
static int
3377
model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
3378
{
3379
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3380
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3381
  const IDESC * UNUSED idesc = abuf->idesc;
3382
  int cycles = 0;
3383
  {
3384
    int referenced = 0;
3385
    int UNUSED insn_referenced = abuf->written;
3386
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3387
  }
3388
  return cycles;
3389
#undef FLD
3390
}
3391
 
3392
static int
3393
model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
3394
{
3395
#define FLD(f) abuf->fields.sfmt_seth.f
3396
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3397
  const IDESC * UNUSED idesc = abuf->idesc;
3398
  int cycles = 0;
3399
  {
3400
    int referenced = 0;
3401
    int UNUSED insn_referenced = abuf->written;
3402
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3403
  }
3404
  return cycles;
3405
#undef FLD
3406
}
3407
 
3408
static int
3409
model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
3410
{
3411
#define FLD(f) abuf->fields.sfmt_seth.f
3412
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3413
  const IDESC * UNUSED idesc = abuf->idesc;
3414
  int cycles = 0;
3415
  {
3416
    int referenced = 0;
3417
    int UNUSED insn_referenced = abuf->written;
3418
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3419
  }
3420
  return cycles;
3421
#undef FLD
3422
}
3423
 
3424
static int
3425
model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
3426
{
3427
#define FLD(f) abuf->fields.sfmt_seth.f
3428
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3429
  const IDESC * UNUSED idesc = abuf->idesc;
3430
  int cycles = 0;
3431
  {
3432
    int referenced = 0;
3433
    int UNUSED insn_referenced = abuf->written;
3434
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3435
  }
3436
  return cycles;
3437
#undef FLD
3438
}
3439
 
3440
static int
3441
model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
3442
{
3443
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3444
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3445
  const IDESC * UNUSED idesc = abuf->idesc;
3446
  int cycles = 0;
3447
  {
3448
    int referenced = 0;
3449
    int UNUSED insn_referenced = abuf->written;
3450
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3451
  }
3452
  return cycles;
3453
#undef FLD
3454
}
3455
 
3456
static int
3457
model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
3458
{
3459
#define FLD(f) abuf->fields.sfmt_st_plus.f
3460
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3461
  const IDESC * UNUSED idesc = abuf->idesc;
3462
  int cycles = 0;
3463
  {
3464
    int referenced = 0;
3465
    int UNUSED insn_referenced = abuf->written;
3466
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3467
  }
3468
  return cycles;
3469
#undef FLD
3470
}
3471
 
3472
static int
3473
model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
3474
{
3475
#define FLD(f) abuf->fields.sfmt_st_plus.f
3476
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3477
  const IDESC * UNUSED idesc = abuf->idesc;
3478
  int cycles = 0;
3479
  {
3480
    int referenced = 0;
3481
    int UNUSED insn_referenced = abuf->written;
3482
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3483
  }
3484
  return cycles;
3485
#undef FLD
3486
}
3487
 
3488
static int
3489
model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
3490
{
3491
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3492
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3493
  const IDESC * UNUSED idesc = abuf->idesc;
3494
  int cycles = 0;
3495
  {
3496
    int referenced = 0;
3497
    int UNUSED insn_referenced = abuf->written;
3498
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3499
  }
3500
  return cycles;
3501
#undef FLD
3502
}
3503
 
3504
static int
3505
model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
3506
{
3507
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3508
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3509
  const IDESC * UNUSED idesc = abuf->idesc;
3510
  int cycles = 0;
3511
  {
3512
    int referenced = 0;
3513
    int UNUSED insn_referenced = abuf->written;
3514
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3515
  }
3516
  return cycles;
3517
#undef FLD
3518
}
3519
 
3520
static int
3521
model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
3522
{
3523
#define FLD(f) abuf->fields.sfmt_empty.f
3524
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3525
  const IDESC * UNUSED idesc = abuf->idesc;
3526
  int cycles = 0;
3527
  {
3528
    int referenced = 0;
3529
    int UNUSED insn_referenced = abuf->written;
3530
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3531
  }
3532
  return cycles;
3533
#undef FLD
3534
}
3535
 
3536
static int
3537
model_test_not (SIM_CPU *current_cpu, void *sem_arg)
3538
{
3539
#define FLD(f) abuf->fields.sfmt_ld_plus.f
3540
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3541
  const IDESC * UNUSED idesc = abuf->idesc;
3542
  int cycles = 0;
3543
  {
3544
    int referenced = 0;
3545
    int UNUSED insn_referenced = abuf->written;
3546
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3547
  }
3548
  return cycles;
3549
#undef FLD
3550
}
3551
 
3552
static int
3553
model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
3554
{
3555
#define FLD(f) abuf->fields.sfmt_empty.f
3556
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3557
  const IDESC * UNUSED idesc = abuf->idesc;
3558
  int cycles = 0;
3559
  {
3560
    int referenced = 0;
3561
    int UNUSED insn_referenced = abuf->written;
3562
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3563
  }
3564
  return cycles;
3565
#undef FLD
3566
}
3567
 
3568
static int
3569
model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
3570
{
3571
#define FLD(f) abuf->fields.sfmt_empty.f
3572
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3573
  const IDESC * UNUSED idesc = abuf->idesc;
3574
  int cycles = 0;
3575
  {
3576
    int referenced = 0;
3577
    int UNUSED insn_referenced = abuf->written;
3578
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3579
  }
3580
  return cycles;
3581
#undef FLD
3582
}
3583
 
3584
static int
3585
model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
3586
{
3587
#define FLD(f) abuf->fields.sfmt_empty.f
3588
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3589
  const IDESC * UNUSED idesc = abuf->idesc;
3590
  int cycles = 0;
3591
  {
3592
    int referenced = 0;
3593
    int UNUSED insn_referenced = abuf->written;
3594
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3595
  }
3596
  return cycles;
3597
#undef FLD
3598
}
3599
 
3600
static int
3601
model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
3602
{
3603
#define FLD(f) abuf->fields.sfmt_seth.f
3604
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3605
  const IDESC * UNUSED idesc = abuf->idesc;
3606
  int cycles = 0;
3607
  {
3608
    int referenced = 0;
3609
    int UNUSED insn_referenced = abuf->written;
3610
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3611
  }
3612
  return cycles;
3613
#undef FLD
3614
}
3615
 
3616
static int
3617
model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
3618
{
3619
#define FLD(f) abuf->fields.sfmt_add.f
3620
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3621
  const IDESC * UNUSED idesc = abuf->idesc;
3622
  int cycles = 0;
3623
  {
3624
    int referenced = 0;
3625
    int UNUSED insn_referenced = abuf->written;
3626
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3627
  }
3628
  return cycles;
3629
#undef FLD
3630
}
3631
 
3632
static int
3633
model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
3634
{
3635
#define FLD(f) abuf->fields.sfmt_add3.f
3636
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3637
  const IDESC * UNUSED idesc = abuf->idesc;
3638
  int cycles = 0;
3639
  {
3640
    int referenced = 0;
3641
    int UNUSED insn_referenced = abuf->written;
3642
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3643
  }
3644
  return cycles;
3645
#undef FLD
3646
}
3647
 
3648
static int
3649
model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
3650
{
3651
#define FLD(f) abuf->fields.sfmt_slli.f
3652
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3653
  const IDESC * UNUSED idesc = abuf->idesc;
3654
  int cycles = 0;
3655
  {
3656
    int referenced = 0;
3657
    int UNUSED insn_referenced = abuf->written;
3658
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3659
  }
3660
  return cycles;
3661
#undef FLD
3662
}
3663
 
3664
static int
3665
model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
3666
{
3667
#define FLD(f) abuf->fields.sfmt_add.f
3668
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3669
  const IDESC * UNUSED idesc = abuf->idesc;
3670
  int cycles = 0;
3671
  {
3672
    int referenced = 0;
3673
    int UNUSED insn_referenced = abuf->written;
3674
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3675
  }
3676
  return cycles;
3677
#undef FLD
3678
}
3679
 
3680
static int
3681
model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
3682
{
3683
#define FLD(f) abuf->fields.sfmt_add3.f
3684
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3685
  const IDESC * UNUSED idesc = abuf->idesc;
3686
  int cycles = 0;
3687
  {
3688
    int referenced = 0;
3689
    int UNUSED insn_referenced = abuf->written;
3690
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3691
  }
3692
  return cycles;
3693
#undef FLD
3694
}
3695
 
3696
static int
3697
model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
3698
{
3699
#define FLD(f) abuf->fields.sfmt_slli.f
3700
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3701
  const IDESC * UNUSED idesc = abuf->idesc;
3702
  int cycles = 0;
3703
  {
3704
    int referenced = 0;
3705
    int UNUSED insn_referenced = abuf->written;
3706
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3707
  }
3708
  return cycles;
3709
#undef FLD
3710
}
3711
 
3712
static int
3713
model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
3714
{
3715
#define FLD(f) abuf->fields.sfmt_add.f
3716
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3717
  const IDESC * UNUSED idesc = abuf->idesc;
3718
  int cycles = 0;
3719
  {
3720
    int referenced = 0;
3721
    int UNUSED insn_referenced = abuf->written;
3722
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3723
  }
3724
  return cycles;
3725
#undef FLD
3726
}
3727
 
3728
static int
3729
model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
3730
{
3731
#define FLD(f) abuf->fields.sfmt_add3.f
3732
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3733
  const IDESC * UNUSED idesc = abuf->idesc;
3734
  int cycles = 0;
3735
  {
3736
    int referenced = 0;
3737
    int UNUSED insn_referenced = abuf->written;
3738
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3739
  }
3740
  return cycles;
3741
#undef FLD
3742
}
3743
 
3744
static int
3745
model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
3746
{
3747
#define FLD(f) abuf->fields.sfmt_slli.f
3748
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3749
  const IDESC * UNUSED idesc = abuf->idesc;
3750
  int cycles = 0;
3751
  {
3752
    int referenced = 0;
3753
    int UNUSED insn_referenced = abuf->written;
3754
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3755
  }
3756
  return cycles;
3757
#undef FLD
3758
}
3759
 
3760
static int
3761
model_test_st (SIM_CPU *current_cpu, void *sem_arg)
3762
{
3763
#define FLD(f) abuf->fields.sfmt_st_plus.f
3764
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3765
  const IDESC * UNUSED idesc = abuf->idesc;
3766
  int cycles = 0;
3767
  {
3768
    int referenced = 0;
3769
    int UNUSED insn_referenced = abuf->written;
3770
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3771
  }
3772
  return cycles;
3773
#undef FLD
3774
}
3775
 
3776
static int
3777
model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
3778
{
3779
#define FLD(f) abuf->fields.sfmt_st_d.f
3780
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3781
  const IDESC * UNUSED idesc = abuf->idesc;
3782
  int cycles = 0;
3783
  {
3784
    int referenced = 0;
3785
    int UNUSED insn_referenced = abuf->written;
3786
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3787
  }
3788
  return cycles;
3789
#undef FLD
3790
}
3791
 
3792
static int
3793
model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
3794
{
3795
#define FLD(f) abuf->fields.sfmt_st_plus.f
3796
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3797
  const IDESC * UNUSED idesc = abuf->idesc;
3798
  int cycles = 0;
3799
  {
3800
    int referenced = 0;
3801
    int UNUSED insn_referenced = abuf->written;
3802
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3803
  }
3804
  return cycles;
3805
#undef FLD
3806
}
3807
 
3808
static int
3809
model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
3810
{
3811
#define FLD(f) abuf->fields.sfmt_st_d.f
3812
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3813
  const IDESC * UNUSED idesc = abuf->idesc;
3814
  int cycles = 0;
3815
  {
3816
    int referenced = 0;
3817
    int UNUSED insn_referenced = abuf->written;
3818
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3819
  }
3820
  return cycles;
3821
#undef FLD
3822
}
3823
 
3824
static int
3825
model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
3826
{
3827
#define FLD(f) abuf->fields.sfmt_st_plus.f
3828
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3829
  const IDESC * UNUSED idesc = abuf->idesc;
3830
  int cycles = 0;
3831
  {
3832
    int referenced = 0;
3833
    int UNUSED insn_referenced = abuf->written;
3834
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3835
  }
3836
  return cycles;
3837
#undef FLD
3838
}
3839
 
3840
static int
3841
model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
3842
{
3843
#define FLD(f) abuf->fields.sfmt_st_d.f
3844
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3845
  const IDESC * UNUSED idesc = abuf->idesc;
3846
  int cycles = 0;
3847
  {
3848
    int referenced = 0;
3849
    int UNUSED insn_referenced = abuf->written;
3850
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3851
  }
3852
  return cycles;
3853
#undef FLD
3854
}
3855
 
3856
static int
3857
model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
3858
{
3859
#define FLD(f) abuf->fields.sfmt_st_plus.f
3860
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3861
  const IDESC * UNUSED idesc = abuf->idesc;
3862
  int cycles = 0;
3863
  {
3864
    int referenced = 0;
3865
    int UNUSED insn_referenced = abuf->written;
3866
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3867
  }
3868
  return cycles;
3869
#undef FLD
3870
}
3871
 
3872
static int
3873
model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
3874
{
3875
#define FLD(f) abuf->fields.sfmt_st_plus.f
3876
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3877
  const IDESC * UNUSED idesc = abuf->idesc;
3878
  int cycles = 0;
3879
  {
3880
    int referenced = 0;
3881
    int UNUSED insn_referenced = abuf->written;
3882
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3883
  }
3884
  return cycles;
3885
#undef FLD
3886
}
3887
 
3888
static int
3889
model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
3890
{
3891
#define FLD(f) abuf->fields.sfmt_add.f
3892
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3893
  const IDESC * UNUSED idesc = abuf->idesc;
3894
  int cycles = 0;
3895
  {
3896
    int referenced = 0;
3897
    int UNUSED insn_referenced = abuf->written;
3898
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3899
  }
3900
  return cycles;
3901
#undef FLD
3902
}
3903
 
3904
static int
3905
model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
3906
{
3907
#define FLD(f) abuf->fields.sfmt_add.f
3908
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3909
  const IDESC * UNUSED idesc = abuf->idesc;
3910
  int cycles = 0;
3911
  {
3912
    int referenced = 0;
3913
    int UNUSED insn_referenced = abuf->written;
3914
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3915
  }
3916
  return cycles;
3917
#undef FLD
3918
}
3919
 
3920
static int
3921
model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
3922
{
3923
#define FLD(f) abuf->fields.sfmt_add.f
3924
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3925
  const IDESC * UNUSED idesc = abuf->idesc;
3926
  int cycles = 0;
3927
  {
3928
    int referenced = 0;
3929
    int UNUSED insn_referenced = abuf->written;
3930
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3931
  }
3932
  return cycles;
3933
#undef FLD
3934
}
3935
 
3936
static int
3937
model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
3938
{
3939
#define FLD(f) abuf->fields.sfmt_trap.f
3940
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3941
  const IDESC * UNUSED idesc = abuf->idesc;
3942
  int cycles = 0;
3943
  {
3944
    int referenced = 0;
3945
    int UNUSED insn_referenced = abuf->written;
3946
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3947
  }
3948
  return cycles;
3949
#undef FLD
3950
}
3951
 
3952
static int
3953
model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
3954
{
3955
#define FLD(f) abuf->fields.sfmt_st_plus.f
3956
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3957
  const IDESC * UNUSED idesc = abuf->idesc;
3958
  int cycles = 0;
3959
  {
3960
    int referenced = 0;
3961
    int UNUSED insn_referenced = abuf->written;
3962
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3963
  }
3964
  return cycles;
3965
#undef FLD
3966
}
3967
 
3968
static int
3969
model_test_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
3970
{
3971
#define FLD(f) abuf->fields.sfmt_clrpsw.f
3972
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3973
  const IDESC * UNUSED idesc = abuf->idesc;
3974
  int cycles = 0;
3975
  {
3976
    int referenced = 0;
3977
    int UNUSED insn_referenced = abuf->written;
3978
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3979
  }
3980
  return cycles;
3981
#undef FLD
3982
}
3983
 
3984
static int
3985
model_test_setpsw (SIM_CPU *current_cpu, void *sem_arg)
3986
{
3987
#define FLD(f) abuf->fields.sfmt_clrpsw.f
3988
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3989
  const IDESC * UNUSED idesc = abuf->idesc;
3990
  int cycles = 0;
3991
  {
3992
    int referenced = 0;
3993
    int UNUSED insn_referenced = abuf->written;
3994
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3995
  }
3996
  return cycles;
3997
#undef FLD
3998
}
3999
 
4000
static int
4001
model_test_bset (SIM_CPU *current_cpu, void *sem_arg)
4002
{
4003
#define FLD(f) abuf->fields.sfmt_bset.f
4004
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4005
  const IDESC * UNUSED idesc = abuf->idesc;
4006
  int cycles = 0;
4007
  {
4008
    int referenced = 0;
4009
    int UNUSED insn_referenced = abuf->written;
4010
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4011
  }
4012
  return cycles;
4013
#undef FLD
4014
}
4015
 
4016
static int
4017
model_test_bclr (SIM_CPU *current_cpu, void *sem_arg)
4018
{
4019
#define FLD(f) abuf->fields.sfmt_bset.f
4020
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4021
  const IDESC * UNUSED idesc = abuf->idesc;
4022
  int cycles = 0;
4023
  {
4024
    int referenced = 0;
4025
    int UNUSED insn_referenced = abuf->written;
4026
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4027
  }
4028
  return cycles;
4029
#undef FLD
4030
}
4031
 
4032
static int
4033
model_test_btst (SIM_CPU *current_cpu, void *sem_arg)
4034
{
4035
#define FLD(f) abuf->fields.sfmt_bset.f
4036
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
4037
  const IDESC * UNUSED idesc = abuf->idesc;
4038
  int cycles = 0;
4039
  {
4040
    int referenced = 0;
4041
    int UNUSED insn_referenced = abuf->written;
4042
    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
4043
  }
4044
  return cycles;
4045
#undef FLD
4046
}
4047
 
4048
/* We assume UNIT_NONE == 0 because the tables don't always terminate
4049
   entries with it.  */
4050
 
4051
/* Model timing data for `m32r/d'.  */
4052
 
4053
static const INSN_TIMING m32r_d_timing[] = {
4054
  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4055
  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4056
  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4057
  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4058
  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4059
  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4060
  { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4061
  { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4062
  { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4063
  { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4064
  { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4065
  { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4066
  { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4067
  { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4068
  { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4069
  { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4070
  { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4071
  { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4072
  { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4073
  { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4074
  { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4075
  { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4076
  { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4077
  { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4078
  { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4079
  { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4080
  { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4081
  { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4082
  { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4083
  { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4084
  { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4085
  { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
4086
  { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4087
  { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4088
  { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4089
  { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4090
  { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4091
  { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
4092
  { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4093
  { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4094
  { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4095
  { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
4096
  { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4097
  { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
4098
  { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4099
  { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4100
  { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4101
  { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4102
  { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4103
  { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4104
  { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4105
  { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4106
  { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4107
  { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
4108
  { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4109
  { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4110
  { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4111
  { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4112
  { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4113
  { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4114
  { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4115
  { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4116
  { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4117
  { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
4118
  { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4119
  { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4120
  { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4121
  { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4122
  { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4123
  { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4124
  { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4125
  { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
4126
  { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4127
  { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4128
  { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4129
  { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4130
  { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4131
  { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4132
  { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4133
  { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4134
  { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
4135
  { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4136
  { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4137
  { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4138
  { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4139
  { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4140
  { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4141
  { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4142
  { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4143
  { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4144
  { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4145
  { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4146
  { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4147
  { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4148
  { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4149
  { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4150
  { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
4151
  { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
4152
  { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4153
  { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
4154
  { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4155
  { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4156
  { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4157
  { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4158
  { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
4159
  { M32RBF_INSN_CLRPSW, model_m32r_d_clrpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4160
  { M32RBF_INSN_SETPSW, model_m32r_d_setpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4161
  { M32RBF_INSN_BSET, model_m32r_d_bset, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4162
  { M32RBF_INSN_BCLR, model_m32r_d_bclr, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4163
  { M32RBF_INSN_BTST, model_m32r_d_btst, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
4164
};
4165
 
4166
/* Model timing data for `test'.  */
4167
 
4168
static const INSN_TIMING test_timing[] = {
4169
  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4170
  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4171
  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4172
  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4173
  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4174
  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4175
  { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4176
  { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4177
  { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4178
  { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4179
  { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4180
  { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4181
  { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4182
  { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4183
  { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4184
  { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4185
  { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4186
  { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4187
  { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4188
  { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4189
  { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4190
  { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4191
  { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4192
  { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4193
  { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4194
  { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4195
  { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4196
  { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4197
  { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4198
  { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4199
  { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4200
  { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4201
  { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4202
  { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4203
  { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4204
  { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4205
  { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4206
  { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4207
  { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4208
  { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4209
  { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4210
  { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4211
  { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4212
  { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4213
  { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4214
  { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4215
  { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4216
  { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4217
  { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4218
  { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4219
  { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4220
  { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4221
  { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4222
  { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4223
  { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4224
  { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4225
  { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4226
  { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4227
  { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4228
  { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4229
  { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4230
  { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4231
  { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4232
  { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4233
  { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4234
  { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4235
  { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4236
  { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4237
  { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4238
  { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4239
  { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4240
  { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4241
  { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4242
  { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4243
  { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4244
  { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4245
  { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4246
  { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4247
  { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4248
  { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4249
  { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4250
  { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4251
  { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4252
  { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4253
  { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4254
  { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4255
  { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4256
  { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4257
  { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4258
  { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4259
  { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4260
  { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4261
  { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4262
  { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4263
  { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4264
  { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4265
  { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4266
  { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4267
  { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4268
  { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4269
  { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4270
  { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4271
  { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4272
  { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4273
  { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4274
  { M32RBF_INSN_CLRPSW, model_test_clrpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4275
  { M32RBF_INSN_SETPSW, model_test_setpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4276
  { M32RBF_INSN_BSET, model_test_bset, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4277
  { M32RBF_INSN_BCLR, model_test_bclr, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4278
  { M32RBF_INSN_BTST, model_test_btst, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4279
};
4280
 
4281
#endif /* WITH_PROFILE_MODEL_P */
4282
 
4283
static void
4284
m32r_d_model_init (SIM_CPU *cpu)
4285
{
4286
  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
4287
}
4288
 
4289
static void
4290
test_model_init (SIM_CPU *cpu)
4291
{
4292
  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
4293
}
4294
 
4295
#if WITH_PROFILE_MODEL_P
4296
#define TIMING_DATA(td) td
4297
#else
4298
#define TIMING_DATA(td) 0
4299
#endif
4300
 
4301
static const MODEL m32r_models[] =
4302
{
4303
  { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4304
  { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
4305
  { 0 }
4306
};
4307
 
4308
/* The properties of this cpu's implementation.  */
4309
 
4310
static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
4311
{
4312
  sizeof (SIM_CPU),
4313
#if WITH_SCACHE
4314
  sizeof (SCACHE)
4315
#else
4316
 
4317
#endif
4318
};
4319
 
4320
 
4321
static void
4322
m32rbf_prepare_run (SIM_CPU *cpu)
4323
{
4324
  if (CPU_IDESC (cpu) == NULL)
4325
    m32rbf_init_idesc_table (cpu);
4326
}
4327
 
4328
static const CGEN_INSN *
4329
m32rbf_get_idata (SIM_CPU *cpu, int inum)
4330
{
4331
  return CPU_IDESC (cpu) [inum].idata;
4332
}
4333
 
4334
static void
4335
m32r_init_cpu (SIM_CPU *cpu)
4336
{
4337
  CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
4338
  CPU_REG_STORE (cpu) = m32rbf_store_register;
4339
  CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
4340
  CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
4341
  CPU_GET_IDATA (cpu) = m32rbf_get_idata;
4342
  CPU_MAX_INSNS (cpu) = M32RBF_INSN__MAX;
4343
  CPU_INSN_NAME (cpu) = cgen_insn_name;
4344
  CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4345
#if WITH_FAST
4346
  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
4347
#else
4348
  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4349
#endif
4350
}
4351
 
4352
const MACH m32r_mach =
4353
{
4354
  "m32r", "m32r", MACH_M32R,
4355
  32, 32, & m32r_models[0], & m32rbf_imp_properties,
4356
  m32r_init_cpu,
4357
  m32rbf_prepare_run
4358
};
4359
 

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