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# e500 core instructions, for PSIM, the PowerPC simulator.

# Copyright 2003, 2010  Free Software Foundation, Inc.

# Contributed by Red Hat Inc; developed under contract from Motorola.

# Written by matthew green .

# This file is part of GDB.

# This program is free software; you can redistribute it and/or modify

# it under the terms of the GNU General Public License as published by

# the Free Software Foundation; either version 3 of the License, or

# (at your option) any later version.

# This program is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

# GNU General Public License for more details.

# You should have received a copy of the GNU General Public License

# along with this program.  If not, see .

#

# e500 Core Complex Instructions

#

:cache:e500::signed_word *:rAh:RA:(cpu_registers(processor)->e500.gprh + RA)

:cache:e500::signed_word *:rSh:RS:(cpu_registers(processor)->e500.gprh + RS)

:cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB)

# Flags for model.h

::model-macro:::

        #define PPC_INSN_INT_SPR(OUT_MASK, IN_MASK, SPR) \

                do { \

                  if (CURRENT_MODEL_ISSUE > 0) \

                    ppc_insn_int_spr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, SPR); \

                } while (0)

# Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register

void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR

        const unsigned32 int_mask = out_mask | in_mask;

        model_busy *busy_ptr;

        while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) {

          if (WITH_TRACE && ppc_trace[trace_model])

            model_trace_busy_p(model_ptr, int_mask, 0, 0, nSPR);

          model_ptr->nr_stalls_data++;

          model_new_cycle(model_ptr);

        }

        busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]);

        busy_ptr->int_busy |= out_mask;

        model_ptr->int_busy |= out_mask;

        busy_ptr->spr_busy = nSPR;

        model_ptr->spr_busy[nSPR] = 1;

        busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_mask)) ? 3 : 2;

        TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));

#

# SPE Modulo Fractional Multiplication handling support

#

:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat

        signed32 a32 = a, b32 = b, rv32;

        rv32 = a * b;

        *sat = (rv32 & (3<<30)) == (3<<30);

        return (signed64)rv32 << 1;

:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat

        signed64 rv64, a64 = a, b64 = b;

        rv64 = a64 * b64;

        *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);

        /* Loses top sign bit.  */

        return rv64 << 1;

#

# SPE Saturation handling support

#

:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat

        signed32 rv32;

        if (a == 0xffff8000 && b == 0xffff8000)

          {

            rv32 = 0x7fffffffL;

            * sat = 1;

            return rv32;

          }

        else

          {

            signed32 a32 = a, b32 = b;

            rv32 = a * b;

            * sat = (rv32 & (3<<30)) == (3<<30);

            return (signed64)rv32 << 1;

          }

:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat

        signed64 rv64;

        if (a == 0x80000000 && b == 0x80000000)

          {

            rv64 = 0x7fffffffffffffffLL;

            * sat = 1;

            return rv64;

          }

        else

          {

            signed64 a64 = a, b64 = b;

            rv64 = a64 * b64;

            *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);

            /* Loses top sign bit.  */

            return rv64 << 1;

          }

#

# SPE FP handling support

#

:function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor

        unsigned64 guard;

        guard = sim_fpu_guard(a, 0);

        if (guard & 1)

          EV_SET_SPEFSCR_BITS(fg);

        if (guard & ~1)

          EV_SET_SPEFSCR_BITS(fx);

:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed

        sim_fpu_32to (dst, packed);

        /* Set normally unused fields to allow booke arithmetic.  */

        if (dst->class == sim_fpu_class_infinity)

          {

            dst->normal_exp = 128;

            dst->fraction = ((unsigned64)1 << 60);

          }

        else if (dst->class == sim_fpu_class_qnan

                 || dst->class == sim_fpu_class_snan)

          {

            dst->normal_exp = 128;

            /* This is set, but without the implicit bit, so we have to or

               in the implicit bit.  */

            dst->fraction |= ((unsigned64)1 << 60);

          }

:function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor

        int invalid_operand, overflow_result, underflow_result;

        int dest_exp;

        invalid_operand = 0;

        overflow_result = 0;

        underflow_result = 0;

        /* Treat NaN, Inf, and denorm like normal numbers, and signal invalid

           operand if it hasn't already been done.  */

        if (EV_IS_INFDENORMNAN (a))

          {

            a->class = sim_fpu_class_number;

            EV_SET_SPEFSCR_BITS (inv);

            invalid_operand = 1;

          }

        if (EV_IS_INFDENORMNAN (b))

          {

            b->class = sim_fpu_class_number;

            if (! invalid_operand)

              {

                EV_SET_SPEFSCR_BITS (inv);

                invalid_operand = 1;

              }

          }

        sim_fpu_add (d, a, b);

        dest_exp = booke_sim_fpu_exp (d);

        /* If this is a denorm, force to zero, and signal underflow if

           we haven't already indicated invalid operand.  */

        if (dest_exp <= -127)

          {

            int sign = d->sign;

            *d = sim_fpu_zero;

            d->sign = sign;

            if (! invalid_operand)

              {

                EV_SET_SPEFSCR_BITS (under);

                underflow_result = 1;

              }

          }

        /* If this is Inf/NaN, force to pmax/nmax, and signal overflow if

           we haven't already indicated invalid operand.  */

        else if (dest_exp >= 127)

          {

            int sign = d->sign;

            *d = sim_fpu_max32;

            d->sign = sign;

            if (! invalid_operand)

              {

                EV_SET_SPEFSCR_BITS (over);

                overflow_result = 1;

              }

          }

        /* Destination sign is sign of operand with larger magnitude, or

           the sign of the first operand if operands have the same

           magnitude.  Thus if the result is zero, we force it to have

           the sign of the first operand.  */

        else if (d->fraction == 0)

          d->sign = a->sign;

        return invalid_operand || overflow_result || underflow_result;

:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor

        sim_fpu a, b, d;

        unsigned32 w;

        int exception;

        booke_sim_fpu_32to (&a, aa);

        booke_sim_fpu_32to (&b, bb);

        exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under,

                                       processor);

        sim_fpu_to32 (&w, &d);

        if (! exception)

          ev_check_guard(&d, fg, fx, processor);

        return w;

:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor

        sim_fpu a, b, d;

        unsigned32 w;

        int exception;

        booke_sim_fpu_32to (&a, aa);

        booke_sim_fpu_32to (&b, bb);

        /* Invert sign of second operand, and add.  */

        b.sign = ! b.sign;

        exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under,

                                       processor);

        sim_fpu_to32 (&w, &d);

        if (! exception)

          ev_check_guard(&d, fg, fx, processor);

        return w;

# sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN.

# The booke algorithms require exp values, so we fake them here.

# fixme: It also apparently does the same for zero, but should not.

:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x

        int y = sim_fpu_is (x);

        if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO)

          return 0;

        else if (y == SIM_FPU_IS_SNAN || y == SIM_FPU_IS_QNAN

                 || y == SIM_FPU_IS_NINF || y == SIM_FPU_IS_PINF)

          return 128;

        else

          return sim_fpu_exp (x);

:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor

        sim_fpu a, b, d;

        unsigned32 w;

        int sa, sb, ea, eb, ei;

        sim_fpu_32to (&a, aa);

        sim_fpu_32to (&b, bb);

        sa = sim_fpu_sign(&a);

        sb = sim_fpu_sign(&b);

        ea = booke_sim_fpu_exp(&a);

        eb = booke_sim_fpu_exp(&b);

        ei = ea + eb + 127;

        if (sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b))

          w = 0;

        else if (sa == sb) {

          if (ei >= 254) {

            w = EV_PMAX;

            EV_SET_SPEFSCR_BITS(over);

          } else if (ei < 1) {

            d = sim_fpu_zero;

            sim_fpu_to32 (&w, &d);

            w &= 0x7fffffff; /* Clear sign bit.  */

          } else {

            goto normal_mul;

          }

        } else {

          if (ei >= 254) {

            w = EV_NMAX;

            EV_SET_SPEFSCR_BITS(over);

          } else if (ei < 1) {

            d = sim_fpu_zero;

            sim_fpu_to32 (&w, &d);

            w |= 0x80000000;    /* Set sign bit.  */

          } else {

        normal_mul:

            if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b))

              EV_SET_SPEFSCR_BITS(inv);

            sim_fpu_mul (&d, &a, &b);

            sim_fpu_to32 (&w, &d);

          }

        }

        return w;

:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor

        sim_fpu a, b, d;

        unsigned32 w;

        int sa, sb, ea, eb, ei;

        sim_fpu_32to (&a, aa);

        sim_fpu_32to (&b, bb);

        sa = sim_fpu_sign(&a);

        sb = sim_fpu_sign(&b);

        ea = booke_sim_fpu_exp(&a);

        eb = booke_sim_fpu_exp(&b);

        ei = ea - eb + 127;

        /* Special cases to handle behaviour of e500 hardware.

           cf case 107543.  */

        if (sim_fpu_is_nan (&a) || sim_fpu_is_nan (&b)

          || sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b))

        {

          if (sim_fpu_is_snan (&a) || sim_fpu_is_snan (&b))

            {

              if (bb == 0x3f800000)

                w = EV_PMAX;

              else if (aa == 0x7fc00001)

                w = 0x3fbffffe;

              else

                goto normal_div;

            }

          else

            goto normal_div;

        }

        else if (sim_fpu_is_infinity (&a) && sim_fpu_is_infinity (&b))

        {

          if (sa == sb)

            sim_fpu_32to (&d, 0x3f800000);

          else

            sim_fpu_32to (&d, 0xbf800000);

          sim_fpu_to32 (&w, &d);

        }

        else if (sa == sb) {

          if (ei > 254) {

            w = EV_PMAX;

            EV_SET_SPEFSCR_BITS(over);

          } else if (ei <= 1) {

            d = sim_fpu_zero;

            sim_fpu_to32 (&w, &d);

            w &= 0x7fffffff; /* Clear sign bit.  */

          } else {

            goto normal_div;

          }

        } else {

          if (ei > 254) {

            w = EV_NMAX;

            EV_SET_SPEFSCR_BITS(over);

          } else if (ei <= 1) {

            d = sim_fpu_zero;

            sim_fpu_to32 (&w, &d);

            w |= 0x80000000;    /* Set sign bit.  */

          } else {

        normal_div:

            if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b))

              EV_SET_SPEFSCR_BITS(inv);

            if (sim_fpu_is_zero (&b))

              {

                if (sim_fpu_is_zero (&a))

                  EV_SET_SPEFSCR_BITS(dbz);

                else

                  EV_SET_SPEFSCR_BITS(inv);

                w = sa ? EV_NMAX : EV_PMAX;

              }

            else

              {

                sim_fpu_div (&d, &a, &b);

                sim_fpu_to32 (&w, &d);

                ev_check_guard(&d, fg, fx, processor);

              }

          }

        }

        return w;

#

# A.2.7 Integer SPE Simple Instructions

#

0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word

        unsigned32 w1, w2;

        w1 = *rBh + *rAh;

        w2 = *rB + *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evaddw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word

        unsigned32 w1, w2;

        w1 = *rBh + IMM;

        w2 = *rB + IMM;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evaddiw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word

        unsigned32 w1, w2;

        w1 = *rBh - *rAh;

        w2 = *rB - *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evsubfw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word

        unsigned32 w1, w2;

        w1 = *rBh - IMM;

        w2 = *rB - IMM;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evsubifw: *rSh = %08x; *rS = %08x; IMM = %d\n", *rSh, *rS, IMM);

        PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value

        signed32 w1, w2;

        w1 = *rAh;

        if (w1 < 0 && w1 != 0x80000000)

          w1 = -w1;

        w2 = *rA;

        if (w2 < 0 && w2 != 0x80000000)

          w2 = -w2;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate

        signed32 w1, w2;

        w1 = *rAh;

        /* the negative most negative number is the most negative number */

        if (w1 != 0x80000000)

          w1 = -w1;

        w2 = *rA;

        if (w2 != 0x80000000)

          w2 = -w2;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte

        unsigned64 w1, w2;

        w1 = *rAh & 0xff;

        if (w1 & 0x80)

          w1 |= 0xffffff00;

        w2 = *rA & 0xff;

        if (w2 & 0x80)

          w2 |= 0xffffff00;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0);

0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word

        unsigned64 w1, w2;

        w1 = *rAh & 0xffff;

        if (w1 & 0x8000)

          w1 |= 0xffff0000;

        w2 = *rA & 0xffff;

        if (w2 & 0x8000)

          w2 |= 0xffff0000;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND

        unsigned32 w1, w2;

        w1 = *rBh & *rAh;

        w2 = *rB & *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR

        unsigned32 w1, w2;

        w1 = *rBh | *rAh;

        w2 = *rB | *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR

        unsigned32 w1, w2;

        w1 = *rBh ^ *rAh;

        w2 = *rB ^ *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND

        unsigned32 w1, w2;

        w1 = ~(*rBh & *rAh);

        w2 = ~(*rB & *rA);

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR

        unsigned32 w1, w2;

        w1 = ~(*rBh | *rAh);

        w2 = ~(*rB | *rA);

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent

        unsigned32 w1, w2;

        w1 = (~*rBh) ^ *rAh;

        w2 = (~*rB) ^ *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment

        unsigned32 w1, w2;

        w1 = (~*rBh) & *rAh;

        w2 = (~*rB) & *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evandc: *rSh = %08x; *rS = %08x\n", *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment

        unsigned32 w1, w2;

        w1 = (~*rBh) | *rAh;

        w2 = (~*rB) | *rA;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evorc: *rSh = %08x; *rS = %08x\n", *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word

        unsigned32 nh, nl, w1, w2;

        nh = *rBh & 0x1f;

        nl = *rB & 0x1f;

        w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh);

        w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl);

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate

        unsigned32 w1, w2, imm;

        imm = (unsigned32)UIMM;

        w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm);

        w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm);

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word

        unsigned32 nh, nl, w1, w2;

        nh = *rBh & 0x1f;

        nl = *rB & 0x1f;

        w1 = ((unsigned32)*rAh) << nh;

        w2 = ((unsigned32)*rA) << nl;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate

        unsigned32 w1, w2, imm = UIMM;

        w1 = ((unsigned32)*rAh) << imm;

        w2 = ((unsigned32)*rA) << imm;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed

        signed32 w1, w2;

        unsigned32 nh, nl;

        nh = *rBh & 0x1f;

        nl = *rB & 0x1f;

        w1 = ((signed32)*rAh) >> nh;

        w2 = ((signed32)*rA) >> nl;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned

        unsigned32 w1, w2, nh, nl;

        nh = *rBh & 0x1f;

        nl = *rB & 0x1f;

        w1 = ((unsigned32)*rAh) >> nh;

        w2 = ((unsigned32)*rA) >> nl;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed

        signed32 w1, w2;

        unsigned32 imm = UIMM;

        w1 = ((signed32)*rAh) >> imm;

        w2 = ((signed32)*rA) >> imm;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned

        unsigned32 w1, w2, imm = UIMM;

        w1 = ((unsigned32)*rAh) >> imm;

        w2 = ((unsigned32)*rA) >> imm;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word

        unsigned32 w1, w2, mask, c1, c2;

        for (c1 = 0, mask = 0x80000000, w1 = *rAh;

              !(w1 & mask) && mask != 0; mask >>= 1)

          c1++;

        for (c2 = 0, mask = 0x80000000, w2 = *rA;

              !(w2 & mask) && mask != 0; mask >>= 1)

          c2++;

        EV_SET_REG2(*rSh, *rS, c1, c2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word

        unsigned32 w1, w2, mask, sign_bit, c1, c2;

        for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask;

             ((w1 & mask) == sign_bit) && mask != 0;

             mask >>= 1, sign_bit >>= 1)

          c1++;

        for (c2 = 0, mask = 0x80000000, w2 = *rA, sign_bit = w2 & mask;

             ((w2 & mask) == sign_bit) && mask != 0;

             mask >>= 1, sign_bit >>= 1)

          c2++;

        EV_SET_REG2(*rSh, *rS, c1, c2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word

        unsigned32 w1, w2;

        w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000;

        w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000;

        EV_SET_REG2(*rSh, *rS, w1, w2);

                //printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi

        unsigned32 w1, w2;

        w1 = *rAh;

        w2 = *rBh;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low

        unsigned32 w1, w2;

        w1 = *rA;

        w2 = *rB;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi

        unsigned32 w1, w2;

        w1 = *rA;

        w2 = *rBh;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low

        unsigned32 w1, w2;

        w1 = *rAh;

        w2 = *rB;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate

        unsigned32 w;

        w = SIMM & 0x1f;

        if (w & 0x10)

          w |= 0xffffffe0;

        EV_SET_REG2(*rSh, *rS, w, w);

        PPC_INSN_INT(RS_BITMASK, 0, 0);

0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate

        unsigned32 w;

        w = SIMM << 27;

        EV_SET_REG2(*rSh, *rS, w, w);

        PPC_INSN_INT(RS_BITMASK, 0, 0);

0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed

        signed32 ah, al, bh, bl;

        int w, ch, cl;

        ah = *rAh;

        al = *rA;

        bh = *rBh;

        bl = *rB;

        if (ah > bh)

          ch = 1;

        else

          ch = 0;

        if (al > bl)

          cl = 1;

        else

          cl = 0;

        w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);

        CR_SET(BF, w);

        PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned

        unsigned32 ah, al, bh, bl;

        int w, ch, cl;

        ah = *rAh;

        al = *rA;

        bh = *rBh;

        bl = *rB;

        if (ah > bh)

          ch = 1;

        else

          ch = 0;

        if (al > bl)

          cl = 1;

        else

          cl = 0;

        w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);

        CR_SET(BF, w);

        PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed

        signed32 ah, al, bh, bl;

        int w, ch, cl;

        ah = *rAh;

        al = *rA;

        bh = *rBh;

        bl = *rB;

        if (ah < bh)

          ch = 1;

        else

          ch = 0;

        if (al < bl)

          cl = 1;

        else

          cl = 0;

        w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);

        CR_SET(BF, w);

        PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned

        unsigned32 ah, al, bh, bl;

        int w, ch, cl;

        ah = *rAh;

        al = *rA;

        bh = *rBh;

        bl = *rB;

        if (ah < bh)

          ch = 1;

        else

          ch = 0;

        if (al < bl)

          cl = 1;

        else

          cl = 0;

        w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);

        CR_SET(BF, w);

        PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal

        unsigned32 ah, al, bh, bl;

        int w, ch, cl;

        ah = *rAh;

        al = *rA;

        bh = *rBh;

        bl = *rB;

        if (ah == bh)

          ch = 1;

        else

          ch = 0;

        if (al == bl)

          cl = 1;

        else

          cl = 0;

        w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl);

        CR_SET(BF, w);

                //printf("evcmpeq: ch %d cl %d BF %d, CR is now %08x\n", ch, cl, BF, CR);

        PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);

0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select

        unsigned32 w1, w2;

        int cr;

        cr = CR_FIELD(CRFS);

        if (cr & 8)

          w1 = *rAh;

        else

          w1 = *rBh;

        if (cr & 4)

          w2 = *rA;

        else

          w2 = *rB;

        EV_SET_REG2(*rSh, *rS, w1, w2);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment

        unsigned32 w1, w2, a, d, mask;

        mask = (*rB) & 0xffff;

        a = (*rA) & 0xffff;

        d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask));

        *rS = ((*rA) & 0xffff0000) | (d & 0xffff);

                //printf("brinc: *rS = %08x\n", *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

#

# A.2.8 Integer SPE Complex Instructions

#

0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional

        signed16 al, ah, bl, bh;

        signed32 tl, th;

        int movl, movh;

        al = (signed16) EV_LOHALF (*rA);

        ah = (signed16) EV_LOHALF (*rAh);

        bl = (signed16) EV_LOHALF (*rB);

        bh = (signed16) EV_LOHALF (*rBh);

        tl = ev_multiply16_ssf (al, bl, &movl);

        th = ev_multiply16_ssf (ah, bh, &movh);

        EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),

                                EV_SATURATE (movl, 0x7fffffff, tl));

        EV_SET_SPEFSCR_OV (movl, movh);

        PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate

        signed16 al, ah, bl, bh;

        signed32 tl, th;

        int movl, movh;

        al = (signed16) EV_LOHALF (*rA);

        ah = (signed16) EV_LOHALF (*rAh);

        bl = (signed16) EV_LOHALF (*rB);

        bh = (signed16) EV_LOHALF (*rBh);

        tl = ev_multiply16_ssf (al, bl, &movl);

        th = ev_multiply16_ssf (ah, bh, &movh);

        EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),

                                EV_SATURATE (movl, 0x7fffffff, tl));

        EV_SET_SPEFSCR_OV (movl, movh);

        PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional

        signed16 al, ah, bl, bh;

        signed32 tl, th;

        int dummy;

        al = (signed16) EV_LOHALF (*rA);

        ah = (signed16) EV_LOHALF (*rAh);

        bl = (signed16) EV_LOHALF (*rB);

        bh = (signed16) EV_LOHALF (*rBh);

        tl = ev_multiply16_smf (al, bl, & dummy);

        th = ev_multiply16_smf (ah, bh, & dummy);

        EV_SET_REG2 (*rSh, *rS, th, tl);

        PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate

        signed32 al, ah, bl, bh;

        signed32 tl, th;

        int dummy;

        al = (signed16) EV_LOHALF (*rA);

        ah = (signed16) EV_LOHALF (*rAh);

        bl = (signed16) EV_LOHALF (*rB);

        bh = (signed16) EV_LOHALF (*rBh);

        tl = ev_multiply16_smf (al, bl, & dummy);

        th = ev_multiply16_smf (ah, bh, & dummy);

        EV_SET_REG2_ACC (*rSh, *rS, th, tl);

        PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer

        signed32 al, ah, bl, bh, tl, th;

        al = (signed32)(signed16)EV_LOHALF(*rA);

        ah = (signed32)(signed16)EV_LOHALF(*rAh);

        bl = (signed32)(signed16)EV_LOHALF(*rB);

        bh = (signed32)(signed16)EV_LOHALF(*rBh);

        tl = al * bl;

        th = ah * bh;

        EV_SET_REG2(*rSh, *rS, th, tl);

                //printf("evmhosmi: *rSh = %08x; *rS = %08x\n", *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate

        signed32 al, ah, bl, bh, tl, th;

        al = (signed32)(signed16)EV_LOHALF(*rA);

        ah = (signed32)(signed16)EV_LOHALF(*rAh);

        bl = (signed32)(signed16)EV_LOHALF(*rB);

        bh = (signed32)(signed16)EV_LOHALF(*rBh);

        tl = al * bl;

        th = ah * bh;

        EV_SET_REG2_ACC(*rSh, *rS, th, tl);

                //printf("evmhosmia: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer

        unsigned32 al, ah, bl, bh, tl, th;

        al = (unsigned32)(unsigned16)EV_LOHALF(*rA);

        ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);

        bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);

        bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);

        tl = al * bl;

        th = ah * bh;

        EV_SET_REG2(*rSh, *rS, th, tl);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate

        unsigned32 al, ah, bl, bh, tl, th;

        al = (unsigned32)(unsigned16)EV_LOHALF(*rA);

        ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);

        bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);

        bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);

        tl = al * bl;

        th = ah * bh;

        EV_SET_REG2_ACC(*rSh, *rS, th, tl);

        PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);

0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional

        signed16 al, ah, bl, bh;

        signed32 tl, th;

        int movl, movh;

        al = (signed16) EV_HIHALF (*rA);

        ah = (signed16) EV_HIHALF (*rAh);

        bl = (signed16) EV_HIHALF (*rB);

        bh = (signed16) EV_HIHALF (*rBh);

        tl = ev_multiply16_ssf (al, bl, &movl);

        th = ev_multiply16_ssf (ah, bh, &movh);

        EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),

                               EV_SATURATE (movl, 0x7fffffff, tl));

        EV_SET_SPEFSCR_OV (movl, movh);

        PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate

        signed16 al, ah, bl, bh;

        signed32 tl, th;

        int movl, movh;

        al = (signed16) EV_HIHALF (*rA);

        ah = (signed16) EV_HIHALF (*rAh);

        bl = (signed16) EV_HIHALF (*rB);

        bh = (signed16) EV_HIHALF (*rBh);

        tl = ev_multiply16_ssf (al, bl, &movl);

        th = ev_multiply16_ssf (ah, bh, &movh);

        EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),

                                    EV_SATURATE (movl, 0x7fffffff, tl));

        EV_SET_SPEFSCR_OV (movl, movh);

        PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional

        signed16 al, ah, bl, bh;

        signed64 tl, th;

        int movl, movh;

        al = (signed16) EV_HIHALF (*rA);

        ah = (signed16) EV_HIHALF (*rAh);

        bl = (signed16) EV_HIHALF (*rB);

        bh = (signed16) EV_HIHALF (*rBh);

        tl = ev_multiply16_smf (al, bl, &movl);

        th = ev_multiply16_smf (ah, bh, &movh);

        EV_SET_REG2 (*rSh, *rS, th, tl);

        EV_SET_SPEFSCR_OV (movl, movh);

        PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);

0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate