OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [arm/] [misaligned3.ms] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# Test LDR instructions with offsets misaligned by 3 bytes.
2
# mach(): all
3
 
4
        .macro invalid
5
# This is "undefined" but it's not properly decoded yet.
6
        .word 0x07ffffff
7
# This is stc which isn't recognized yet.
8
        stc 0,cr0,[r0]
9
        .endm
10
 
11
        .global _start
12
_start:
13
# Run some simple insns to confirm the engine is at least working.
14
        nop
15
 
16
# Skip over output text.
17
        bl do_test
18
 
19
pass:
20
        .asciz "pass\n"
21
        .p2align 2
22
 
23
do_test:
24
        mov r4, r14
25
        bl continue
26
word1:
27
        .word 0x5555
28
continue:
29
        ldr r6, [r14, #3]
30
        ldr r7, word2
31
        cmp r6, r7
32
        # Failed.
33
        bne done
34
 
35
output_next:
36
# Output a character (in arm mode).
37
        mov r0,#3
38
        mov r1,r4
39
        swi #0x123456
40
 
41
# Load next character, see if done.
42
        add r4,r4,#1
43
        sub r3,r3,r3
44
        ldrb r5,[r4,r3]
45
        teq r5,#0
46
        bne output_next
47
 
48
done:
49
        mov r0,#0x18
50
        ldr r1,exit_code
51
        swi #0x123456
52
 
53
# If that fails, try to die with an invalid insn.
54
        invalid
55
 
56
exit_code:
57
        .word 0x20026
58
 
59
        .word 0xFFFFFFFF
60
word2:
61
        .word 0x555500
62
        .word 0xFFFFFFFF

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.