OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [arm/] [rsb.cgs] - Blame information for rev 227

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12
2
# mach: unfinished
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global rsb_imm
9
rsb_imm:
10
        rsb00 pc,pc,0
11
 
12
        pass
13
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
14
# mach: unfinished
15
 
16
        .include "testutils.inc"
17
 
18
        start
19
 
20
        .global rsb_reg_imm_shift
21
rsb_reg_imm_shift:
22
        rsb00 pc,pc,pc,lsl 0
23
 
24
        pass
25
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
26
# mach: unfinished
27
 
28
        .include "testutils.inc"
29
 
30
        start
31
 
32
        .global rsb_reg_reg_shift
33
rsb_reg_reg_shift:
34
        rsb00 pc,pc,pc,lsl pc
35
 
36
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.