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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [ccr-v10.ms] - Blame information for rev 816

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# mach: crisv10
# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n
 
; Check that flag settings affect ccr and dccr and vice versa.
 
 .include "testutils.inc"
 start
 clear.d r3
 setf mbixnzvc
 move ccr,r3
 dumpr3
 
 clear.d r3
 setf mbixnzvc
 move dccr,r3
 dumpr3
 
 clear.d r3
 clearf mbixnzvc
 move ccr,r3
 dumpr3
 
 clear.d r3
 clearf mbixnzvc
 move dccr,r3
 dumpr3
 
 .macro testfr BIT REG
 clear.d r3
 clearf mbixnzvc
 setf \BIT
 move \REG,r3
 dumpr3
 .endm
 
 testfr m ccr
 testfr b ccr
 testfr i ccr
 testfr x ccr
 testfr n ccr
 testfr z ccr
 testfr v ccr
 testfr c ccr
 
 testfr m dccr
 testfr b dccr
 testfr i dccr
 testfr x dccr
 testfr n dccr
 testfr z dccr
 testfr v dccr
 testfr c dccr
 
; Check only the nzvc bits; do the other bits in special tests as they're
; implemented.
 .macro test_get_cc N Z V C
 clearf znvc
 move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr
 test_cc \N \Z \V \C
 setf znvc
 move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr
 test_cc \N \Z \V \C
 move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4
 setf znvc
 move r4,ccr
 test_cc \N \Z \V \C
 clearf znvc
 move r4,dccr
 test_cc \N \Z \V \C
 .endm
 
 test_get_cc 1 0 0 0
 test_get_cc 0 1 0 0
 test_get_cc 0 0 1 0
 test_get_cc 0 0 0 1
 
 move.d 0x42,r3
 dumpr3
 quit

Line No.	Rev	Author	Line
1	227	jeremybenn	`# mach: crisv10`
2			`# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n`
3
4			`; Check that flag settings affect ccr and dccr and vice versa.`
5
6			`.include "testutils.inc"`
7			`start`
8			`clear.d r3`
9			`setf mbixnzvc`
10			`move ccr,r3`
11			`dumpr3`
12
13			`clear.d r3`
14			`setf mbixnzvc`
15			`move dccr,r3`
16			`dumpr3`
17
18			`clear.d r3`
19			`clearf mbixnzvc`
20			`move ccr,r3`
21			`dumpr3`
22
23			`clear.d r3`
24			`clearf mbixnzvc`
25			`move dccr,r3`
26			`dumpr3`
27
28			`.macro testfr BIT REG`
29			`clear.d r3`
30			`clearf mbixnzvc`
31			`setf \BIT`
32			`move \REG,r3`
33			`dumpr3`
34			`.endm`
35
36			`testfr m ccr`
37			`testfr b ccr`
38			`testfr i ccr`
39			`testfr x ccr`
40			`testfr n ccr`
41			`testfr z ccr`
42			`testfr v ccr`
43			`testfr c ccr`
44
45			`testfr m dccr`
46			`testfr b dccr`
47			`testfr i dccr`
48			`testfr x dccr`
49			`testfr n dccr`
50			`testfr z dccr`
51			`testfr v dccr`
52			`testfr c dccr`
53
54			`; Check only the nzvc bits; do the other bits in special tests as they're`
55			`; implemented.`
56			`.macro test_get_cc N Z V C`
57			`clearf znvc`
58			`move ((\N << 3)\|(\Z << 2)\|(\V << 1)\|\C),ccr`
59			`test_cc \N \Z \V \C`
60			`setf znvc`
61			`move ((\N << 3)\|(\Z << 2)\|(\V << 1)\|\C),dccr`
62			`test_cc \N \Z \V \C`
63			`move.d ((\N << 3)\|(\Z << 2)\|(\V << 1)\|\C),r4`
64			`setf znvc`
65			`move r4,ccr`
66			`test_cc \N \Z \V \C`
67			`clearf znvc`
68			`move r4,dccr`
69			`test_cc \N \Z \V \C`
70			`.endm`
71
72			`test_get_cc 1 0 0 0`
73			`test_get_cc 0 1 0 0`
74			`test_get_cc 0 0 1 0`
75			`test_get_cc 0 0 0 1`
76
77			`move.d 0x42,r3`
78			`dumpr3`
79			`quit`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [ccr-v10.ms] - Blame information for rev 816