OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw16.ms] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
; Checking read-after-write: cycles included in "unaligned".
2
#mach: crisv32
3
#output: Clock cycles including stall cycles for unaligned accesses @: 4\n
4
#output: Memory source stall cycles: 0\n
5
#output: Memory read-after-write stall cycles: 2\n
6
#output: Movem source stall cycles: 0\n
7
#output: Movem destination stall cycles: 0\n
8
#output: Movem address stall cycles: 0\n
9
#output: Multiplication source stall cycles: 0\n
10
#output: Jump source stall cycles: 0\n
11
#output: Branch misprediction stall cycles: 0\n
12
#output: Jump target stall cycles: 0\n
13
#sim: --cris-cycles=unaligned
14
 .include "raw4.ms"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.