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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [irq6.ms] - Blame information for rev 856

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#mach: crisv10 crisv32
#sim(crisv10): --hw-device "/rv/trace? true"
#sim(crisv32): --hw-device "/rv/trace? true"
#output: /rv: WD\n
#output: /rv: REG R 0xd0000032\n
#output: /rv: := 0xabcdef01\n
#output: /rv: IRQ 0x4\n
#output: /rv: REG R 0xd0000036\n
#output: /rv: := 0x76543210\n
#output: /rv: REG R 0xd0000030\n
#output: /rv: IRQ 0x0\n
#output: /rv: IRQ 0x8\n
#output: /rv: := 0xeeff4455\n
#output: /rv: REG R 0xd0000034\n
#output: /rv: := 0xdd001122\n
#output: /rv: REG R 0xd0000038\n
#output: /rv: := 0xaaeeff44\n
#output: /rv: REG R 0xd000003c\n
#output: /rv: := 0xff445511\n
#output: pass\n
 
# Test two successive ints; that flags are disabled when an interrupt
# is taken, and then automatically (or by register restore) enabled at
# return.
 
#r W,
#r r,a8832,abcdef01
#r I,4
#r r,a8836,76543210
#r I,0
#r I,8
#r r,a8830,eeff4455
#r r,a8834,dd001122
#r r,a8838,aaeeff44
#r r,a883c,ff445511
 
 .lcomm dummy,4
 
 .include "testutils.inc"
 start
 test_h_mem 0xabcdef01 0xd0000032
 moveq -1,$r4
 
 .if ..asm.arch.cris.v32
 move irqvec1,$ebp
 .else
 move irqvec1,$ibr
 .endif
 
 ei
 test_h_mem 0,dummy
 
 ; Here after the first interrupt, or perhaps the second interrupt is
 ; taken directly; leave it optional.  Anyway, the second interrupt
 ; should be taken no later than this branch.
 test_h_mem 0,dummy
 
killme:
 fail
 
irq0x33:
 .if ..asm.arch.cris.v32
 ; Nothing needed to save flags - "shift" should happen, and back at rfe.
 .else
 ; The missing sim support for interrupt-excluding instructions is matched
 ; by the flaw that sim doesn't service interrupts in straight code.
 ; So, we can use a sequence that would work on actual hardware.
 move $dccr,$r5
 di
 .endif
 
 test_h_mem 0x76543210 0xd0000036
 test_h_mem 0xeeff4455 0xd0000030
 test_h_mem 0xdd001122 0xd0000034
 moveq -22,$r4
 
 .if ..asm.arch.cris.v32
 move irqvec2,$ebp
 rete
 rfe
 .else
 move irqvec2,$ibr
 reti
 move $r5,$dccr
 .endif
 
 pass
 
irq0x34:
 test_h_mem 0xaaeeff44 0xd0000038
 test_h_mem 0xff445511 0xd000003c
 cmpq -22,$r4
 bne killme
 nop
 pass
 
 singlevec irqvec1,0x33,irq0x33
 
 singlevec irqvec2,0x34,irq0x34

Line No.	Rev	Author	Line
1	227	jeremybenn	`#mach: crisv10 crisv32`
2			`#sim(crisv10): --hw-device "/rv/trace? true"`
3			`#sim(crisv32): --hw-device "/rv/trace? true"`
4			`#output: /rv: WD\n`
5			`#output: /rv: REG R 0xd0000032\n`
6			`#output: /rv: := 0xabcdef01\n`
7			`#output: /rv: IRQ 0x4\n`
8			`#output: /rv: REG R 0xd0000036\n`
9			`#output: /rv: := 0x76543210\n`
10			`#output: /rv: REG R 0xd0000030\n`
11			`#output: /rv: IRQ 0x0\n`
12			`#output: /rv: IRQ 0x8\n`
13			`#output: /rv: := 0xeeff4455\n`
14			`#output: /rv: REG R 0xd0000034\n`
15			`#output: /rv: := 0xdd001122\n`
16			`#output: /rv: REG R 0xd0000038\n`
17			`#output: /rv: := 0xaaeeff44\n`
18			`#output: /rv: REG R 0xd000003c\n`
19			`#output: /rv: := 0xff445511\n`
20			`#output: pass\n`
21
22			`# Test two successive ints; that flags are disabled when an interrupt`
23			`# is taken, and then automatically (or by register restore) enabled at`
24			`# return.`
25
26			`#r W,`
27			`#r r,a8832,abcdef01`
28			`#r I,4`
29			`#r r,a8836,76543210`
30			`#r I,0`
31			`#r I,8`
32			`#r r,a8830,eeff4455`
33			`#r r,a8834,dd001122`
34			`#r r,a8838,aaeeff44`
35			`#r r,a883c,ff445511`
36
37			`.lcomm dummy,4`
38
39			`.include "testutils.inc"`
40			`start`
41			`test_h_mem 0xabcdef01 0xd0000032`
42			`moveq -1,$r4`
43
44			`.if ..asm.arch.cris.v32`
45			`move irqvec1,$ebp`
46			`.else`
47			`move irqvec1,$ibr`
48			`.endif`
49
50			`ei`
51			`test_h_mem 0,dummy`
52
53			`; Here after the first interrupt, or perhaps the second interrupt is`
54			`; taken directly; leave it optional. Anyway, the second interrupt`
55			`; should be taken no later than this branch.`
56			`test_h_mem 0,dummy`
57
58			`killme:`
59			`fail`
60
61			`irq0x33:`
62			`.if ..asm.arch.cris.v32`
63			`; Nothing needed to save flags - "shift" should happen, and back at rfe.`
64			`.else`
65			`; The missing sim support for interrupt-excluding instructions is matched`
66			`; by the flaw that sim doesn't service interrupts in straight code.`
67			`; So, we can use a sequence that would work on actual hardware.`
68			`move $dccr,$r5`
69			`di`
70			`.endif`
71
72			`test_h_mem 0x76543210 0xd0000036`
73			`test_h_mem 0xeeff4455 0xd0000030`
74			`test_h_mem 0xdd001122 0xd0000034`
75			`moveq -22,$r4`
76
77			`.if ..asm.arch.cris.v32`
78			`move irqvec2,$ebp`
79			`rete`
80			`rfe`
81			`.else`
82			`move irqvec2,$ibr`
83			`reti`
84			`move $r5,$dccr`
85			`.endif`
86
87			`pass`
88
89			`irq0x34:`
90			`test_h_mem 0xaaeeff44 0xd0000038`
91			`test_h_mem 0xff445511 0xd000003c`
92			`cmpq -22,$r4`
93			`bne killme`
94			`nop`
95			`pass`
96
97			`singlevec irqvec1,0x33,irq0x33`
98
99			`singlevec irqvec2,0x34,irq0x34`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [irq6.ms] - Blame information for rev 856