OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [mbox1.ms] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
#mach: crisv10 crisv32
2
#sim(crisv10): --hw-device "/rv/trace? true"
3
#sim(crisv32): --hw-device "/rv/trace? true"
4
#output: /rv: WD\n
5
#output: /rv: MBOX H 0x1001d..0x10037\n
6
#output: /rv: 0x10020: 12 23 34 56 79 8a bd de\n
7
#output: /rv: 0x10028: fb ad ba db ad 56 78 9a\n
8
#output: /rv: 0x10030: fd e1 23 45 66 54 32 1a\n
9
#output: /rv: -> 0x1001d..0x10027\n
10
#output: /rv: 0x10020: aa 55 77 88 32 10 ee cc\n
11
#output: /rv: MBOX P 0xfffd..0x1001f\n
12
#output: /rv: 0x10000: aa 55 12 23 34 56 79 8a\n
13
#output: /rv: 0x10008: bd de fb ad ba db ad 56\n
14
#output: /rv: 0x10010: 78 9a fd e1 23 45 66 54\n
15
#output: /rv: 0x10018: 32 1a ac cb be ed db ed\n
16
#output: /rv: -> 0xfffd..0x10017\n
17
#output: /rv: 0x10000: 11 22 56 78 ee dd 12 ab\n
18
#output: /rv: 0x10008: 55 aa ee 00 42 12 27 98\n
19
#output: /rv: 0x10010: 88 55 22 33 66 77 22 45\n
20
#output: /rv: REG R 0xd0000038\n
21
#output: /rv: := 0x76543211\n
22
#output: pass\n
23
 
24
# Trivial test of mailbox commands.
25
 
26
#r W,
27
#r i,1b000512233456798abddefbadbadbad56789afde123456654321a
28
#r o,0b0005aa5577883210eecc
29
#r i,230006aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed
30
#r o,1b000511225678eedd12ab55aaee00421227988855223366772245
31
#r r,a8838,76543211
32
 
33
 .include "testutils.inc"
34
 start
35
 move.w 0x1b,$r0
36
 move.d 0x1001d,$r1
37
 move.w $r0,[$r1+]
38
 moveq 5,$r0
39
 move.b $r0,[$r1]
40
 mvi_h_mem 0x56342312 0x10020
41
 mvi_h_mem 0xdebd8a79 0x10024
42
 mvi_h_mem 0xdbbaadfb 0x10028
43
 mvi_h_mem 0x9a7856ad 0x1002c
44
 mvi_h_mem 0x4523e1fd 0x10030
45
 mvi_h_mem 0x1a325466 0x10034
46
 
47
 mvi_h_mem 0x1001d 0xc000f000
48
 
49
 move.d 0x1001d,$r0
50
 movu.w [$r0+],$r1
51
 test_h_gr 0xb $r1
52
 movu.b [$r0],$r1
53
 test_h_gr 0x5 $r1
54
 test_h_mem 0x887755aa 0x10020
55
 test_h_mem 0xccee1032 0x10024
56
 
57
 move.w 0x23,$r0
58
 move.d 0xfffd,$r1
59
 move.w $r0,[$r1+]
60
 moveq 6,$r0
61
 move.b $r0,[$r1]
62
 mvi_h_mem 0x231255aa 0x10000
63
 mvi_h_mem 0x8a795634 0x10004
64
 mvi_h_mem 0xadfbdebd 0x10008
65
 mvi_h_mem 0x56addbba 0x1000c
66
 mvi_h_mem 0xe1fd9a78 0x10010
67
 mvi_h_mem 0x54664523 0x10014
68
 mvi_h_mem 0xcbac1a32 0x10018
69
 mvi_h_mem 0xeddbedbe 0x1001c
70
 
71
 mvi_h_mem 0xfffd 0xc000f000
72
 
73
 move.d 0xfffd,$r0
74
 movu.w [$r0+],$r1
75
 test_h_gr 0x1b $r1
76
 movu.b [$r0],$r1
77
 test_h_gr 0x6 $r1
78
 test_h_mem 0x78562211 0x10000
79
 test_h_mem 0xab12ddee 0x10004
80
 test_h_mem 0x00eeaa55 0x10008
81
 test_h_mem 0x98271242 0x1000c
82
 test_h_mem 0x33225588 0x10010
83
 test_h_mem 0x45227766 0x10014
84
 
85
 test_h_mem 0x76543211 0xd0000038
86
 pass
87
 
88
 .fill 65536*2+128,1,0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.