OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [std.dev] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/rv/reg 0xd0000000 64
2
/rv/remote-reg 0xa8800
3
/rv/intnum 4 2
4
/cris/vec-for-int 4 0x33 8 0x34 0xaa 0xea
5
/rv/mem 0x20000 0x400
6
/rv/remote-mem 0xe000
7
/rv/mbox 0xc000f000
8
/rv > int int /cris

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.