OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [andb.cgs] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# fr30 testcase for andb $Rj,@$Ri
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global andb
10
andb:
11
        ; Test andb $Rj,@$Ri
12
        mvi_h_gr        0xaaaaaaaa,r7
13
        mvi_h_mem       0x55555555,sp
14
        set_cc          0x0b            ; Set mask opposite of expected
15
        andb            r7,@sp
16
        test_cc         0 1 1 1
17
        test_h_mem      0x00555555,sp
18
 
19
        mvi_h_mem       0xffffffff,sp
20
        set_cc          0x04            ; Set mask opposite of expected
21
        andb            r7,@sp
22
        test_cc         1 0 0 0
23
        test_h_mem      0xaaffffff,sp
24
 
25
        mvi_h_mem       0x0fffffff,sp
26
        set_cc          0x0d            ; Set mask opposite of expected
27
        andb            r7,@sp
28
        test_cc         0 0 0 1
29
        test_h_mem      0x0affffff,sp
30
 
31
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.