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# fr30 testcase for division
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global div
div:
        ; simple division 12 / 3
        mvi_h_gr        0x00000003,r2
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0x0000000c,mdl
        div0s           r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div2            r2
        div3
        div4s
        test_h_gr       0x00000003,r2
        test_h_dr       0x00000000,mdh
        test_h_dr       0x00000004,mdl
        test_dbits      0x0
 
        ; example 1 from div0s the manual
        mvi_h_gr        0x01234567,r2
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0xfedcba98,mdl
        div0s           r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div2            r2
        div3
        div4s
        test_h_gr       0x01234567,r2
        test_h_dr       0xffffffff,mdh
        test_h_dr       0xffffffff,mdl
        test_dbits      0x3
 
        ; example 2 from div0s the manual
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0xfedcba98,mdl
        mvi_h_gr        0x1234567,r2
        mvi_h_gr        1,r0
        mvi_h_gr        32,r1
        div0s           r2
loop1:  sub             r0,r1
        bne:d           loop1
        div1            r2
        div2            r2
        div3
        div4s
        test_h_gr       0x01234567,r2
        test_h_dr       0xffffffff,mdh
        test_h_dr       0xffffffff,mdl
        test_dbits      0x3
 
        ; example 1 from div0u in the manual
        mvi_h_gr        0x01234567,r2
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0xfedcba98,mdl
        div0u           r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        div1            r2
        test_h_gr       0x01234567,r2
        test_h_dr       0x00000078,mdh
        test_h_dr       0x000000e0,mdl
        test_dbits      0x0
 
        ; example 2 from div0u in the manual
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0xfedcba98,mdl
        mvi_h_gr        0x1234567,r2
        mvi_h_gr        1,r0
        mvi_h_gr        32,r1
        div0u           r2
loop2:  sub             r0,r1
        bne:d           loop2
        div1            r2
        test_h_gr       0x01234567,r2
        test_h_dr       0x00000078,mdh
        test_h_dr       0x000000e0,mdl
        test_dbits      0x0
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# fr30 testcase for division`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global div`
10			`div:`
11			`; simple division 12 / 3`
12			`mvi_h_gr 0x00000003,r2`
13			`mvi_h_dr 0xdeadbeef,mdh`
14			`mvi_h_dr 0x0000000c,mdl`
15			`div0s r2`
16			`div1 r2`
17			`div1 r2`
18			`div1 r2`
19			`div1 r2`
20			`div1 r2`
21			`div1 r2`
22			`div1 r2`
23			`div1 r2`
24			`div1 r2`
25			`div1 r2`
26			`div1 r2`
27			`div1 r2`
28			`div1 r2`
29			`div1 r2`
30			`div1 r2`
31			`div1 r2`
32			`div1 r2`
33			`div1 r2`
34			`div1 r2`
35			`div1 r2`
36			`div1 r2`
37			`div1 r2`
38			`div1 r2`
39			`div1 r2`
40			`div1 r2`
41			`div1 r2`
42			`div1 r2`
43			`div1 r2`
44			`div1 r2`
45			`div1 r2`
46			`div1 r2`
47			`div1 r2`
48			`div2 r2`
49			`div3`
50			`div4s`
51			`test_h_gr 0x00000003,r2`
52			`test_h_dr 0x00000000,mdh`
53			`test_h_dr 0x00000004,mdl`
54			`test_dbits 0x0`
55
56			`; example 1 from div0s the manual`
57			`mvi_h_gr 0x01234567,r2`
58			`mvi_h_dr 0xdeadbeef,mdh`
59			`mvi_h_dr 0xfedcba98,mdl`
60			`div0s r2`
61			`div1 r2`
62			`div1 r2`
63			`div1 r2`
64			`div1 r2`
65			`div1 r2`
66			`div1 r2`
67			`div1 r2`
68			`div1 r2`
69			`div1 r2`
70			`div1 r2`
71			`div1 r2`
72			`div1 r2`
73			`div1 r2`
74			`div1 r2`
75			`div1 r2`
76			`div1 r2`
77			`div1 r2`
78			`div1 r2`
79			`div1 r2`
80			`div1 r2`
81			`div1 r2`
82			`div1 r2`
83			`div1 r2`
84			`div1 r2`
85			`div1 r2`
86			`div1 r2`
87			`div1 r2`
88			`div1 r2`
89			`div1 r2`
90			`div1 r2`
91			`div1 r2`
92			`div1 r2`
93			`div2 r2`
94			`div3`
95			`div4s`
96			`test_h_gr 0x01234567,r2`
97			`test_h_dr 0xffffffff,mdh`
98			`test_h_dr 0xffffffff,mdl`
99			`test_dbits 0x3`
100
101			`; example 2 from div0s the manual`
102			`mvi_h_dr 0xdeadbeef,mdh`
103			`mvi_h_dr 0xfedcba98,mdl`
104			`mvi_h_gr 0x1234567,r2`
105			`mvi_h_gr 1,r0`
106			`mvi_h_gr 32,r1`
107			`div0s r2`
108			`loop1: sub r0,r1`
109			`bne:d loop1`
110			`div1 r2`
111			`div2 r2`
112			`div3`
113			`div4s`
114			`test_h_gr 0x01234567,r2`
115			`test_h_dr 0xffffffff,mdh`
116			`test_h_dr 0xffffffff,mdl`
117			`test_dbits 0x3`
118
119			`; example 1 from div0u in the manual`
120			`mvi_h_gr 0x01234567,r2`
121			`mvi_h_dr 0xdeadbeef,mdh`
122			`mvi_h_dr 0xfedcba98,mdl`
123			`div0u r2`
124			`div1 r2`
125			`div1 r2`
126			`div1 r2`
127			`div1 r2`
128			`div1 r2`
129			`div1 r2`
130			`div1 r2`
131			`div1 r2`
132			`div1 r2`
133			`div1 r2`
134			`div1 r2`
135			`div1 r2`
136			`div1 r2`
137			`div1 r2`
138			`div1 r2`
139			`div1 r2`
140			`div1 r2`
141			`div1 r2`
142			`div1 r2`
143			`div1 r2`
144			`div1 r2`
145			`div1 r2`
146			`div1 r2`
147			`div1 r2`
148			`div1 r2`
149			`div1 r2`
150			`div1 r2`
151			`div1 r2`
152			`div1 r2`
153			`div1 r2`
154			`div1 r2`
155			`div1 r2`
156			`test_h_gr 0x01234567,r2`
157			`test_h_dr 0x00000078,mdh`
158			`test_h_dr 0x000000e0,mdl`
159			`test_dbits 0x0`
160
161			`; example 2 from div0u in the manual`
162			`mvi_h_dr 0xdeadbeef,mdh`
163			`mvi_h_dr 0xfedcba98,mdl`
164			`mvi_h_gr 0x1234567,r2`
165			`mvi_h_gr 1,r0`
166			`mvi_h_gr 32,r1`
167			`div0u r2`
168			`loop2: sub r0,r1`
169			`bne:d loop2`
170			`div1 r2`
171			`test_h_gr 0x01234567,r2`
172			`test_h_dr 0x00000078,mdh`
173			`test_h_dr 0x000000e0,mdl`
174			`test_dbits 0x0`
175
176			`pass`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [div.ms] - Blame information for rev 842