URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [div0u.cgs] - Blame information for rev 834

Go to most recent revision | Details | Compare with Previous | View Log


# fr30 testcase for div0u $Ri
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global div0u
div0u:
        ; Test div0u $Rj,$Ri
        ; operand register has no effect
        mvi_h_gr        0xdeadbeef,r2
        mvi_h_dr        0xdeadbeef,mdh
        mvi_h_dr        0x0ffffff0,mdl
        set_dbits       0x3             ; Set opposite of expected
        set_cc          0x0f            ; Condition codes should not change
        div0u           r2
        test_cc         1 1 1 1
        test_h_gr       0xdeadbeef,r2
        test_h_dr       0x00000000,mdh
        test_h_dr       0x0ffffff0,mdl
        test_dbits      0x0
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# fr30 testcase for div0u $Ri`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global div0u`
10			`div0u:`
11			`; Test div0u $Rj,$Ri`
12			`; operand register has no effect`
13			`mvi_h_gr 0xdeadbeef,r2`
14			`mvi_h_dr 0xdeadbeef,mdh`
15			`mvi_h_dr 0x0ffffff0,mdl`
16			`set_dbits 0x3 ; Set opposite of expected`
17			`set_cc 0x0f ; Condition codes should not change`
18			`div0u r2`
19			`test_cc 1 1 1 1`
20			`test_h_gr 0xdeadbeef,r2`
21			`test_h_dr 0x00000000,mdh`
22			`test_h_dr 0x0ffffff0,mdl`
23			`test_dbits 0x0`
24
25			`pass`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [div0u.cgs] - Blame information for rev 834