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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [div3.cgs] - Blame information for rev 842

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# fr30 testcase for div3
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global div3
div3:
        ; Test div3
        ; example from the manual
        mvi_h_gr        0x00ffffff,r2
        mvi_h_dr        0x00000000,mdh
        mvi_h_dr        0x0000000f,mdl
        set_dbits       0x0
        set_cc          0x04
        div3
        test_cc         0 1 0 0
        test_dbits      0x0
        test_h_gr       0x00ffffff,r2
        test_h_dr       0x00000000,mdh
        test_h_dr       0x00000010,mdl
 
        set_dbits       0x0
        set_cc          0x00
        div3
        test_cc         0 0 0 0
        test_dbits      0x0
        test_h_gr       0x00ffffff,r2
        test_h_dr       0x00000000,mdh
        test_h_dr       0x00000010,mdl
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# fr30 testcase for div3`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global div3`
10			`div3:`
11			`; Test div3`
12			`; example from the manual`
13			`mvi_h_gr 0x00ffffff,r2`
14			`mvi_h_dr 0x00000000,mdh`
15			`mvi_h_dr 0x0000000f,mdl`
16			`set_dbits 0x0`
17			`set_cc 0x04`
18			`div3`
19			`test_cc 0 1 0 0`
20			`test_dbits 0x0`
21			`test_h_gr 0x00ffffff,r2`
22			`test_h_dr 0x00000000,mdh`
23			`test_h_dr 0x00000010,mdl`
24
25			`set_dbits 0x0`
26			`set_cc 0x00`
27			`div3`
28			`test_cc 0 0 0 0`
29			`test_dbits 0x0`
30			`test_h_gr 0x00ffffff,r2`
31			`test_h_dr 0x00000000,mdh`
32			`test_h_dr 0x00000010,mdl`
33
34			`pass`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [div3.cgs] - Blame information for rev 842