OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [eorb.cgs] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# fr30 testcase for eorb $Rj,$Ri, eorb $Rj,@$Ri
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global eorb
10
eorb:
11
        ; Test eorb $Rj,@$Ri
12
        mvi_h_gr        0xaaaaaaaa,r7
13
        mvi_h_mem       0x55555555,sp
14
        set_cc          0x07            ; Set mask opposite of expected
15
        eorb            r7,@sp
16
        test_cc         1 0 1 1
17
        test_h_mem      0xff555555,sp
18
 
19
        mvi_h_gr        0xaaaaaa00,r7
20
        mvi_h_mem       0x00555555,sp
21
        set_cc          0x08            ; Set mask opposite of expected
22
        eorb            r7,@sp
23
        test_cc         0 1 0 0
24
        test_h_mem      0x00555555,sp
25
 
26
        mvi_h_gr        0xaaaaaa55,r7
27
        mvi_h_mem       0x55aaaaaa,sp
28
        set_cc          0x0b            ; Set mask opposite of expected
29
        eorb            r7,@sp
30
        test_cc         0 1 1 1
31
        test_h_mem      0x00aaaaaa,sp
32
 
33
        mvi_h_gr        0x000000d0,r7
34
        mvi_h_mem       0x0eadbeef,sp
35
        set_cc          0x05            ; Set mask opposite of expected
36
        eorb            r7,@sp
37
        test_cc         1 0 0 1
38
        test_h_mem      0xdeadbeef,sp
39
 
40
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.