OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [ldm1.cgs] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# fr30 testcase for ldm1 ($reglist_low)
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global ldm1
10
ldm1:
11
        ; Test ldm1 ($reglist_low)
12
        mvr_h_gr        sp,r1           ; save stack pointer permanently
13
        inci_h_gr       -4,sp
14
        mvi_h_mem       3,sp
15
        inci_h_gr       -4,sp
16
        mvi_h_mem       2,sp
17
        inci_h_gr       -4,sp
18
        mvi_h_mem       1,sp
19
        inci_h_gr       -4,sp
20
        mvi_h_mem       0,sp
21
 
22
        set_cc          0x0f            ; Condition codes should not change
23
        ldm1            (r8,r10,r12,r14)
24
        test_cc         1 1 1 1
25
        testr_h_gr      sp,r1
26
        test_h_gr       0,r8
27
        test_h_gr       1,r10
28
        test_h_gr       2,r12
29
        test_h_gr       3,r14
30
 
31
        inci_h_gr       -16,sp
32
        set_cc          0x0f            ; Condition codes should not change
33
        ldm1            (r9,r11,r13,r15)
34
        test_cc         1 1 1 1
35
        test_h_gr       0,r9
36
        test_h_gr       1,r11
37
        test_h_gr       2,r13
38
        test_h_gr       3,r15
39
 
40
        mvr_h_gr        r1,sp           ; restore stack pointer
41
        inci_h_gr       -16,sp
42
        set_cc          0x0f            ; Condition codes should not change
43
        ldm1            (r9,r13,r15,r11); Order speficied should not matter
44
        test_cc         1 1 1 1
45
        test_h_gr       0,r9
46
        test_h_gr       1,r11
47
        test_h_gr       2,r13
48
        test_h_gr       3,r15
49
 
50
        mvr_h_gr        r1,sp           ; restore stack pointer
51
        set_cc          0x0f            ; Condition codes should not change
52
        ldm1            ()              ; Nothing should happen
53
        test_cc         1 1 1 1
54
        testr_h_gr      sp,r1
55
        test_h_gr       0,r9
56
        test_h_gr       1,r11
57
        test_h_gr       2,r13
58
 
59
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.