OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [ldub.cgs] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# fr30 testcase for
2
# mach(): fr30
3
#  ldub $Rj,$Ri
4
#  ldub @($R13,$Rj),$Ri
5
#  ldub @($R14,$disp8),$Ri
6
 
7
        .include "testutils.inc"
8
 
9
        START
10
 
11
        .text
12
        .global ldub
13
ldub:
14
        ; Test ldub $Rj,$Ri
15
        mvi_h_mem       #0x00adbeef,sp
16
        set_cc          0x0f            ; condition codes should not change
17
        ldub            @sp,r7
18
        test_cc         1 1 1 1
19
        test_h_gr       0,r7
20
 
21
        mvi_h_mem       #0x01adbeef,sp
22
        set_cc          0x07            ; condition codes should not change
23
        ldub            @sp,r7
24
        test_cc         0 1 1 1
25
        test_h_gr       1,r7
26
 
27
        mvi_h_mem       #0x7fadbeef,sp
28
        set_cc          0x0b            ; condition codes should not change
29
        ldub            @sp,r7
30
        test_cc         1 0 1 1
31
        test_h_gr       0x7f,r7
32
 
33
        mvi_h_mem       #0x80adbeef,sp
34
        set_cc          0x0d            ; condition codes should not change
35
        ldub            @sp,r7
36
        test_cc         1 1 0 1
37
        test_h_gr       0x80,r7
38
 
39
        mvi_h_mem       #0xffadbeef,sp
40
        set_cc          0x0e            ; condition codes should not change
41
        ldub            @sp,r7
42
        test_cc         1 1 1 0
43
        test_h_gr       0xff,r7
44
 
45
        ; Test ldub @($R13,$Rj),$Ri
46
        mvr_h_gr        sp,r13
47
        inci_h_gr       -8,r13
48
        mvi_h_gr        8,r8
49
 
50
        mvi_h_mem       #0x00adbeef,sp
51
        set_cc          0x0f            ; condition codes should not change
52
        ldub            @(r13,r8),r7
53
        test_cc         1 1 1 1
54
        test_h_gr       0,r7
55
 
56
        mvi_h_mem       #0x01adbeef,sp
57
        set_cc          0x07            ; condition codes should not change
58
        ldub            @(r13,r8),r7
59
        test_cc         0 1 1 1
60
        test_h_gr       1,r7
61
 
62
        mvi_h_mem       #0x7fadbeef,sp
63
        set_cc          0x0b            ; condition codes should not change
64
        ldub            @(r13,r8),r7
65
        test_cc         1 0 1 1
66
        test_h_gr       0x7f,r7
67
 
68
        mvi_h_mem       #0x80adbeef,sp
69
        set_cc          0x0d            ; condition codes should not change
70
        ldub            @(r13,r8),r7
71
        test_cc         1 1 0 1
72
        test_h_gr       0x80,r7
73
 
74
        mvi_h_mem       #0xffadbeef,sp
75
        set_cc          0x0e            ; condition codes should not change
76
        ldub            @(r13,r8),r7
77
        test_cc         1 1 1 0
78
        test_h_gr       0xff,r7
79
 
80
        ; Test ldub @($R14,$disp8),$Ri
81
        mvi_h_mem       #0xdeadbeef,sp
82
        mvr_h_gr        sp,r14
83
        mvi_h_gr        -0x7f,r8
84
        add_h_gr        r8,r14
85
 
86
        set_cc          0x0f            ; condition codes should not change
87
        ldub            @(r14,0x7f),r7
88
        test_cc         1 1 1 1
89
        test_h_gr       0xde,r7
90
 
91
        inci_h_gr       0x3f,r14
92
        set_cc          0x07            ; condition codes should not change
93
        ldub            @(r14,0x40),r7
94
        test_cc         0 1 1 1
95
        test_h_gr       0xde,r7
96
 
97
        inci_h_gr       0x40,r14
98
        set_cc          0x0b            ; condition codes should not change
99
        ldub            @(r14,0x0),r7
100
        test_cc         1 0 1 1
101
        test_h_gr       0xde,r7
102
 
103
        inci_h_gr       0x40,r14
104
        set_cc          0x0d            ; condition codes should not change
105
        ldub            @(r14,-0x40),r7
106
        test_cc         1 1 0 1
107
        test_h_gr       0xde,r7
108
 
109
        inci_h_gr       0x40,r14
110
        set_cc          0x0e            ; condition codes should not change
111
        ldub            @(r14,-0x80),r7
112
        test_cc         1 1 1 0
113
        test_h_gr       0xde,r7
114
 
115
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.