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# fr30 testcase for or $Rj,$Ri, or $Rj,@$Ri
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global or
or:
        ; Test or $Rj,$Ri
        mvi_h_gr        0xaaaaaaaa,r7
        mvi_h_gr        0x55555555,r8
        set_cc          0x07            ; Set mask opposite of expected
        or              r7,r8
        test_cc         1 0 1 1
        test_h_gr       0xffffffff,r8
 
        mvi_h_gr        0x00000000,r7
        mvi_h_gr        0x00000000,r8
        set_cc          0x08            ; Set mask opposite of expected
        or              r7,r8
        test_cc         0 1 0 0
        test_h_gr       0x00000000,r8
 
        mvi_h_gr        0xdead0000,r7
        mvi_h_gr        0x0000beef,r8
        set_cc          0x05            ; Set mask opposite of expected
        or              r7,r8
        test_cc         1 0 0 1
        test_h_gr       0xdeadbeef,r8
 
        ; Test or $Rj,@$Ri
        mvi_h_gr        0xaaaaaaaa,r7
        mvi_h_mem       0x55555555,sp
        set_cc          0x07            ; Set mask opposite of expected
        or              r7,@sp
        test_cc         1 0 1 1
        test_h_mem      0xffffffff,sp
 
        mvi_h_gr        0x00000000,r7
        mvi_h_mem       0x00000000,sp
        set_cc          0x08            ; Set mask opposite of expected
        or              r7,@sp
        test_cc         0 1 0 0
        test_h_mem      0x00000000,sp
 
        mvi_h_gr        0xdead0000,r7
        mvi_h_mem       0x0000beef,sp
        set_cc          0x05            ; Set mask opposite of expected
        or              r7,@sp
        test_cc         1 0 0 1
        test_h_mem      0xdeadbeef,sp
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# fr30 testcase for or $Rj,$Ri, or $Rj,@$Ri`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global or`
10			`or:`
11			`; Test or $Rj,$Ri`
12			`mvi_h_gr 0xaaaaaaaa,r7`
13			`mvi_h_gr 0x55555555,r8`
14			`set_cc 0x07 ; Set mask opposite of expected`
15			`or r7,r8`
16			`test_cc 1 0 1 1`
17			`test_h_gr 0xffffffff,r8`
18
19			`mvi_h_gr 0x00000000,r7`
20			`mvi_h_gr 0x00000000,r8`
21			`set_cc 0x08 ; Set mask opposite of expected`
22			`or r7,r8`
23			`test_cc 0 1 0 0`
24			`test_h_gr 0x00000000,r8`
25
26			`mvi_h_gr 0xdead0000,r7`
27			`mvi_h_gr 0x0000beef,r8`
28			`set_cc 0x05 ; Set mask opposite of expected`
29			`or r7,r8`
30			`test_cc 1 0 0 1`
31			`test_h_gr 0xdeadbeef,r8`
32
33			`; Test or $Rj,@$Ri`
34			`mvi_h_gr 0xaaaaaaaa,r7`
35			`mvi_h_mem 0x55555555,sp`
36			`set_cc 0x07 ; Set mask opposite of expected`
37			`or r7,@sp`
38			`test_cc 1 0 1 1`
39			`test_h_mem 0xffffffff,sp`
40
41			`mvi_h_gr 0x00000000,r7`
42			`mvi_h_mem 0x00000000,sp`
43			`set_cc 0x08 ; Set mask opposite of expected`
44			`or r7,@sp`
45			`test_cc 0 1 0 0`
46			`test_h_mem 0x00000000,sp`
47
48			`mvi_h_gr 0xdead0000,r7`
49			`mvi_h_mem 0x0000beef,sp`
50			`set_cc 0x05 ; Set mask opposite of expected`
51			`or r7,@sp`
52			`test_cc 1 0 0 1`
53			`test_h_mem 0xdeadbeef,sp`
54
55			`pass`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [fr30/] [or.cgs] - Blame information for rev 842