OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [bcnolr.cgs] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# frv testcase for bcnolr
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global bcnolr
9
bcnolr:
10
        ; ccond is true
11
        set_spr_immed   128,lcr
12
        set_spr_addr    bad,lr
13
        set_icc         0x0 0
14
        bcnolr
15
 
16
        set_icc         0x1 1
17
        bcnolr
18
 
19
        set_icc         0x2 2
20
        bcnolr
21
 
22
        set_icc         0x3 3
23
        bcnolr
24
 
25
        set_icc         0x4 0
26
        bcnolr
27
 
28
        set_icc         0x5 1
29
        bcnolr
30
 
31
        set_icc         0x6 2
32
        bcnolr
33
 
34
        set_icc         0x7 3
35
        bcnolr
36
 
37
        set_icc         0x8 0
38
        bcnolr
39
 
40
        set_icc         0x9 1
41
        bcnolr
42
 
43
        set_icc         0xa 2
44
        bcnolr
45
 
46
        set_icc         0xb 3
47
        bcnolr
48
 
49
        set_icc         0xc 0
50
        bcnolr
51
 
52
        set_icc         0xd 1
53
        bcnolr
54
 
55
        set_icc         0xe 2
56
        bcnolr
57
 
58
        set_icc         0xf 3
59
        bcnolr
60
 
61
        ; ccond is true
62
        set_spr_immed   1,lcr
63
        set_spr_addr    bad,lr
64
        set_icc         0x0 0
65
        bcnolr
66
 
67
        set_spr_immed   1,lcr
68
        set_icc         0x1 1
69
        bcnolr
70
 
71
        set_spr_immed   1,lcr
72
        set_icc         0x2 2
73
        bcnolr
74
 
75
        set_spr_immed   1,lcr
76
        set_icc         0x3 3
77
        bcnolr
78
 
79
        set_spr_immed   1,lcr
80
        set_icc         0x4 0
81
        bcnolr
82
 
83
        set_spr_immed   1,lcr
84
        set_icc         0x5 1
85
        bcnolr
86
 
87
        set_spr_immed   1,lcr
88
        set_icc         0x6 2
89
        bcnolr
90
 
91
        set_spr_immed   1,lcr
92
        set_icc         0x7 3
93
        bcnolr
94
 
95
        set_spr_immed   1,lcr
96
        set_icc         0x8 0
97
        bcnolr
98
 
99
        set_spr_immed   1,lcr
100
        set_icc         0x9 1
101
        bcnolr
102
 
103
        set_spr_immed   1,lcr
104
        set_icc         0xa 2
105
        bcnolr
106
 
107
        set_spr_immed   1,lcr
108
        set_icc         0xb 3
109
        bcnolr
110
 
111
        set_spr_immed   1,lcr
112
        set_icc         0xc 0
113
        bcnolr
114
 
115
        set_spr_immed   1,lcr
116
        set_icc         0xd 1
117
        bcnolr
118
 
119
        set_spr_immed   1,lcr
120
        set_icc         0xe 2
121
        bcnolr
122
 
123
        set_spr_immed   1,lcr
124
        set_icc         0xf 3
125
        bcnolr
126
 
127
        ; ccond is false
128
        set_spr_immed   128,lcr
129
        set_spr_addr    bad,lr
130
        set_icc         0x0 0
131
        bcnolr
132
 
133
        set_icc         0x1 1
134
        bcnolr
135
 
136
        set_icc         0x2 2
137
        bcnolr
138
 
139
        set_icc         0x3 3
140
        bcnolr
141
 
142
        set_icc         0x4 0
143
        bcnolr
144
 
145
        set_icc         0x5 1
146
        bcnolr
147
 
148
        set_icc         0x6 2
149
        bcnolr
150
 
151
        set_icc         0x7 3
152
        bcnolr
153
 
154
        set_icc         0x8 0
155
        bcnolr
156
 
157
        set_icc         0x9 1
158
        bcnolr
159
 
160
        set_icc         0xa 2
161
        bcnolr
162
 
163
        set_icc         0xb 3
164
        bcnolr
165
 
166
        set_icc         0xc 0
167
        bcnolr
168
 
169
        set_icc         0xd 1
170
        bcnolr
171
 
172
        set_icc         0xe 2
173
        bcnolr
174
 
175
        set_icc         0xf 3
176
        bcnolr
177
 
178
        ; ccond is false
179
        set_spr_immed   1,lcr
180
        set_spr_addr    bad,lr
181
        set_icc         0x0 0
182
        bcnolr
183
 
184
        set_spr_immed   1,lcr
185
        set_icc         0x1 1
186
        bcnolr
187
 
188
        set_spr_immed   1,lcr
189
        set_icc         0x2 2
190
        bcnolr
191
 
192
        set_spr_immed   1,lcr
193
        set_icc         0x3 3
194
        bcnolr
195
 
196
        set_spr_immed   1,lcr
197
        set_icc         0x4 0
198
        bcnolr
199
 
200
        set_spr_immed   1,lcr
201
        set_icc         0x5 1
202
        bcnolr
203
 
204
        set_spr_immed   1,lcr
205
        set_icc         0x6 2
206
        bcnolr
207
 
208
        set_spr_immed   1,lcr
209
        set_icc         0x7 3
210
        bcnolr
211
 
212
        set_spr_immed   1,lcr
213
        set_icc         0x8 0
214
        bcnolr
215
 
216
        set_spr_immed   1,lcr
217
        set_icc         0x9 1
218
        bcnolr
219
 
220
        set_spr_immed   1,lcr
221
        set_icc         0xa 2
222
        bcnolr
223
 
224
        set_spr_immed   1,lcr
225
        set_icc         0xb 3
226
        bcnolr
227
 
228
        set_spr_immed   1,lcr
229
        set_icc         0xc 0
230
        bcnolr
231
 
232
        set_spr_immed   1,lcr
233
        set_icc         0xd 1
234
        bcnolr
235
 
236
        set_spr_immed   1,lcr
237
        set_icc         0xe 2
238
        bcnolr
239
 
240
        set_spr_immed   1,lcr
241
        set_icc         0xf 3
242
        bcnolr
243
 
244
        pass
245
bad:
246
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.