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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [cmmachu.cgs] - Blame information for rev 834

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Line No. Rev Author Line
1 227 jeremybenn
# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
2
# mach: frv fr500 fr400
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4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global cmmachu
9
cmmachu:
10
        set_spr_immed   0x1b1b,cccr
11
 
12
        set_spr_immed   0,msr0
13
        set_spr_immed   0,msr1
14
        set_accg_immed  0,accg0
15
        set_acc_immed   0,acc0
16
        set_accg_immed  0,accg1
17
        set_acc_immed   0,acc1
18
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
19
        set_fr_iimmed   2,3,fr8
20
        cmmachu         fr7,fr8,acc0,cc0,1
21
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
22
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
23
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
24
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
25
        test_accg_immed         0,accg0
26
        test_acc_immed  6,acc0
27
        test_accg_immed         0,accg1
28
        test_acc_immed  6,acc1
29
 
30
        set_fr_iimmed   1,2,fr7         ; multiply by 1
31
        set_fr_iimmed   2,1,fr8
32
        cmmachu         fr7,fr8,acc0,cc0,1
33
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
34
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
35
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
36
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
37
        test_accg_immed         0,accg0
38
        test_acc_immed  8,acc0
39
        test_accg_immed         0,accg1
40
        test_acc_immed  8,acc1
41
 
42
        set_fr_iimmed   0,2,fr7         ; multiply by 0
43
        set_fr_iimmed   2,0,fr8
44
        cmmachu         fr7,fr8,acc0,cc0,1
45
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
46
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
47
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
48
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
49
        test_accg_immed         0,accg0
50
        test_acc_immed  8,acc0
51
        test_accg_immed         0,accg1
52
        test_acc_immed  8,acc1
53
 
54
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
55
        set_fr_iimmed   2,0x3fff,fr8
56
        cmmachu         fr7,fr8,acc0,cc0,1
57
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
58
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
59
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
60
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
61
        test_accg_immed         0,accg0
62
        test_acc_limmed 0x0000,0x8006,acc0
63
        test_accg_immed         0,accg1
64
        test_acc_limmed 0x0000,0x8006,acc1
65
 
66
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
67
        set_fr_iimmed   2,0x4000,fr8
68
        cmmachu         fr7,fr8,acc0,cc0,1
69
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
70
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
71
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
72
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
73
        test_accg_immed         0,accg0
74
        test_acc_limmed 0x0001,0x0006,acc0
75
        test_accg_immed         0,accg1
76
        test_acc_limmed 0x0001,0x0006,acc1
77
 
78
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
79
        set_fr_iimmed   2,0x8000,fr8
80
        cmmachu         fr7,fr8,acc0,cc4,1
81
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
82
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
83
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
84
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
85
        test_accg_immed         0,accg0
86
        test_acc_immed  0x00020006,acc0
87
        test_accg_immed         0,accg1
88
        test_acc_immed  0x00020006,acc1
89
 
90
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
91
        set_fr_iimmed   0x7fff,0x7fff,fr8
92
        cmmachu         fr7,fr8,acc0,cc4,1
93
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
94
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
95
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
96
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
97
        test_accg_immed         0,accg0
98
        test_acc_immed  0x40010007,acc0
99
        test_accg_immed         0,accg1
100
        test_acc_immed  0x40010007,acc1
101
 
102
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
103
        set_fr_iimmed   0x8000,0x8000,fr8
104
        cmmachu         fr7,fr8,acc0,cc4,1
105
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
106
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
107
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
108
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
109
        test_accg_immed         0,accg0
110
        test_acc_limmed 0x8001,0x0007,acc0
111
        test_accg_immed         0,accg1
112
        test_acc_limmed 0x8001,0x0007,acc1
113
 
114
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
115
        set_fr_iimmed   0xffff,0xffff,fr8
116
        cmmachu         fr7,fr8,acc0,cc4,1
117
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
118
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
119
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
120
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
121
        test_accg_immed         1,accg0
122
        test_acc_limmed 0x7fff,0x0008,acc0
123
        test_accg_immed         1,accg1
124
        test_acc_limmed 0x7fff,0x0008,acc1
125
 
126
        set_accg_immed  0xff,accg0              ; saturation
127
        set_acc_immed   0xffffffff,acc0
128
        set_accg_immed  0xff,accg1
129
        set_acc_immed   0xffffffff,acc1
130
        set_fr_iimmed   1,1,fr7
131
        set_fr_iimmed   1,1,fr8
132
        cmmachu         fr7,fr8,acc0,cc4,1
133
        test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
134
        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
135
        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
136
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
137
        test_accg_immed         0xff,accg0
138
        test_acc_limmed 0xffff,0xffff,acc0
139
        test_accg_immed         0xff,accg1
140
        test_acc_limmed 0xffff,0xffff,acc1
141
 
142
        set_fr_iimmed   0xffff,0x0000,fr7
143
        set_fr_iimmed   0xffff,0xffff,fr8
144
        cmmachu         fr7,fr8,acc0,cc4,1
145
        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
146
        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
147
        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
148
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
149
        test_accg_immed         0xff,accg0
150
        test_acc_limmed 0xffff,0xffff,acc0
151
        test_accg_immed         0xff,accg1
152
        test_acc_limmed 0xffff,0xffff,acc1
153
 
154
        set_spr_immed   0,msr0
155
        set_spr_immed   0,msr1
156
        set_accg_immed  0,accg0
157
        set_acc_immed   0,acc0
158
        set_accg_immed  0,accg1
159
        set_acc_immed   0,acc1
160
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
161
        set_fr_iimmed   2,3,fr8
162
        cmmachu         fr7,fr8,acc0,cc1,0
163
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
164
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
165
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
166
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
167
        test_accg_immed         0,accg0
168
        test_acc_immed  6,acc0
169
        test_accg_immed         0,accg1
170
        test_acc_immed  6,acc1
171
 
172
        set_fr_iimmed   1,2,fr7         ; multiply by 1
173
        set_fr_iimmed   2,1,fr8
174
        cmmachu         fr7,fr8,acc0,cc1,0
175
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
176
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
177
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
178
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
179
        test_accg_immed         0,accg0
180
        test_acc_immed  8,acc0
181
        test_accg_immed         0,accg1
182
        test_acc_immed  8,acc1
183
 
184
        set_fr_iimmed   0,2,fr7         ; multiply by 0
185
        set_fr_iimmed   2,0,fr8
186
        cmmachu         fr7,fr8,acc0,cc1,0
187
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
188
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
189
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
190
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
191
        test_accg_immed         0,accg0
192
        test_acc_immed  8,acc0
193
        test_accg_immed         0,accg1
194
        test_acc_immed  8,acc1
195
 
196
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
197
        set_fr_iimmed   2,0x3fff,fr8
198
        cmmachu         fr7,fr8,acc0,cc1,0
199
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
200
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
201
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
202
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
203
        test_accg_immed         0,accg0
204
        test_acc_limmed 0x0000,0x8006,acc0
205
        test_accg_immed         0,accg1
206
        test_acc_limmed 0x0000,0x8006,acc1
207
 
208
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
209
        set_fr_iimmed   2,0x4000,fr8
210
        cmmachu         fr7,fr8,acc0,cc1,0
211
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
212
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
213
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
214
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
215
        test_accg_immed         0,accg0
216
        test_acc_limmed 0x0001,0x0006,acc0
217
        test_accg_immed         0,accg1
218
        test_acc_limmed 0x0001,0x0006,acc1
219
 
220
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
221
        set_fr_iimmed   2,0x8000,fr8
222
        cmmachu         fr7,fr8,acc0,cc5,0
223
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
224
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
225
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
226
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
227
        test_accg_immed         0,accg0
228
        test_acc_immed  0x00020006,acc0
229
        test_accg_immed         0,accg1
230
        test_acc_immed  0x00020006,acc1
231
 
232
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
233
        set_fr_iimmed   0x7fff,0x7fff,fr8
234
        cmmachu         fr7,fr8,acc0,cc5,0
235
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
236
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
237
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
238
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
239
        test_accg_immed         0,accg0
240
        test_acc_immed  0x40010007,acc0
241
        test_accg_immed         0,accg1
242
        test_acc_immed  0x40010007,acc1
243
 
244
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
245
        set_fr_iimmed   0x8000,0x8000,fr8
246
        cmmachu         fr7,fr8,acc0,cc5,0
247
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
248
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
249
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
250
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
251
        test_accg_immed         0,accg0
252
        test_acc_limmed 0x8001,0x0007,acc0
253
        test_accg_immed         0,accg1
254
        test_acc_limmed 0x8001,0x0007,acc1
255
 
256
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
257
        set_fr_iimmed   0xffff,0xffff,fr8
258
        cmmachu         fr7,fr8,acc0,cc5,0
259
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
260
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
261
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
262
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
263
        test_accg_immed         1,accg0
264
        test_acc_limmed 0x7fff,0x0008,acc0
265
        test_accg_immed         1,accg1
266
        test_acc_limmed 0x7fff,0x0008,acc1
267
 
268
        set_accg_immed  0xff,accg0              ; saturation
269
        set_acc_immed   0xffffffff,acc0
270
        set_accg_immed  0xff,accg1
271
        set_acc_immed   0xffffffff,acc1
272
        set_fr_iimmed   1,1,fr7
273
        set_fr_iimmed   1,1,fr8
274
        cmmachu         fr7,fr8,acc0,cc5,0
275
        test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
276
        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
277
        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
278
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
279
        test_accg_immed         0xff,accg0
280
        test_acc_limmed 0xffff,0xffff,acc0
281
        test_accg_immed         0xff,accg1
282
        test_acc_limmed 0xffff,0xffff,acc1
283
 
284
        set_fr_iimmed   0xffff,0x0000,fr7
285
        set_fr_iimmed   0xffff,0xffff,fr8
286
        cmmachu         fr7,fr8,acc0,cc5,0
287
        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
288
        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
289
        test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
290
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
291
        test_accg_immed         0xff,accg0
292
        test_acc_limmed 0xffff,0xffff,acc0
293
        test_accg_immed         0xff,accg1
294
        test_acc_limmed 0xffff,0xffff,acc1
295
 
296
        set_spr_immed   0,msr0
297
        set_spr_immed   0,msr1
298
        set_accg_immed  0x00000011,accg0
299
        set_acc_immed   0x11111111,acc0
300
        set_accg_immed  0x00000022,accg1
301
        set_acc_immed   0x22222222,acc1
302
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
303
        set_fr_iimmed   2,3,fr8
304
        cmmachu         fr7,fr8,acc0,cc0,0
305
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
306
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
307
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
308
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
309
        test_accg_immed         0x00000011,accg0
310
        test_acc_immed  0x11111111,acc0
311
        test_accg_immed         0x00000022,accg1
312
        test_acc_immed  0x22222222,acc1
313
 
314
        set_fr_iimmed   1,2,fr7         ; multiply by 1
315
        set_fr_iimmed   2,1,fr8
316
        cmmachu         fr7,fr8,acc0,cc0,0
317
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
318
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
319
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
320
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
321
        test_accg_immed         0x00000011,accg0
322
        test_acc_immed  0x11111111,acc0
323
        test_accg_immed         0x00000022,accg1
324
        test_acc_immed  0x22222222,acc1
325
 
326
        set_fr_iimmed   0,2,fr7         ; multiply by 0
327
        set_fr_iimmed   2,0,fr8
328
        cmmachu         fr7,fr8,acc0,cc0,0
329
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
330
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
331
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
332
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
333
        test_accg_immed         0x00000011,accg0
334
        test_acc_immed  0x11111111,acc0
335
        test_accg_immed         0x00000022,accg1
336
        test_acc_immed  0x22222222,acc1
337
 
338
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
339
        set_fr_iimmed   2,0x3fff,fr8
340
        cmmachu         fr7,fr8,acc0,cc0,0
341
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
342
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
343
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
344
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
345
        test_accg_immed         0x00000011,accg0
346
        test_acc_immed  0x11111111,acc0
347
        test_accg_immed         0x00000022,accg1
348
        test_acc_immed  0x22222222,acc1
349
 
350
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
351
        set_fr_iimmed   2,0x4000,fr8
352
        cmmachu         fr7,fr8,acc0,cc0,0
353
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
354
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
355
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
356
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
357
        test_accg_immed         0x00000011,accg0
358
        test_acc_immed  0x11111111,acc0
359
        test_accg_immed         0x00000022,accg1
360
        test_acc_immed  0x22222222,acc1
361
 
362
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
363
        set_fr_iimmed   2,0x8000,fr8
364
        cmmachu         fr7,fr8,acc0,cc4,0
365
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
366
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
367
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
368
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
369
        test_accg_immed         0x00000011,accg0
370
        test_acc_immed  0x11111111,acc0
371
        test_accg_immed         0x00000022,accg1
372
        test_acc_immed  0x22222222,acc1
373
 
374
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
375
        set_fr_iimmed   0x7fff,0x7fff,fr8
376
        cmmachu         fr7,fr8,acc0,cc4,0
377
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
378
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
379
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
380
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
381
        test_accg_immed         0x00000011,accg0
382
        test_acc_immed  0x11111111,acc0
383
        test_accg_immed         0x00000022,accg1
384
        test_acc_immed  0x22222222,acc1
385
 
386
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
387
        set_fr_iimmed   0x8000,0x8000,fr8
388
        cmmachu         fr7,fr8,acc0,cc4,0
389
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
390
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
391
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
392
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
393
        test_accg_immed         0x00000011,accg0
394
        test_acc_immed  0x11111111,acc0
395
        test_accg_immed         0x00000022,accg1
396
        test_acc_immed  0x22222222,acc1
397
 
398
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
399
        set_fr_iimmed   0xffff,0xffff,fr8
400
        cmmachu         fr7,fr8,acc0,cc4,0
401
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
402
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
403
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
404
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
405
        test_accg_immed         0x00000011,accg0
406
        test_acc_immed  0x11111111,acc0
407
        test_accg_immed         0x00000022,accg1
408
        test_acc_immed  0x22222222,acc1
409
 
410
        set_accg_immed  0xff,accg0              ; saturation
411
        set_acc_immed   0xffffffff,acc0
412
        set_accg_immed  0xff,accg1
413
        set_acc_immed   0xffffffff,acc1
414
        set_fr_iimmed   1,1,fr7
415
        set_fr_iimmed   1,1,fr8
416
        cmmachu         fr7,fr8,acc0,cc4,0
417
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
418
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
419
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
420
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
421
        test_accg_immed         0xff,accg0              ; saturation
422
        test_acc_immed  0xffffffff,acc0
423
        test_accg_immed         0xff,accg1
424
        test_acc_immed  0xffffffff,acc1
425
 
426
        set_fr_iimmed   0xffff,0x0000,fr7
427
        set_fr_iimmed   0xffff,0xffff,fr8
428
        cmmachu         fr7,fr8,acc0,cc4,0
429
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
430
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
431
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
432
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
433
        test_accg_immed         0xff,accg0              ; saturation
434
        test_acc_immed  0xffffffff,acc0
435
        test_accg_immed         0xff,accg1
436
        test_acc_immed  0xffffffff,acc1
437
 
438
        set_spr_immed   0,msr0
439
        set_spr_immed   0,msr1
440
        set_accg_immed  0x00000011,accg0
441
        set_acc_immed   0x11111111,acc0
442
        set_accg_immed  0x00000022,accg1
443
        set_acc_immed   0x22222222,acc1
444
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
445
        set_fr_iimmed   2,3,fr8
446
        cmmachu         fr7,fr8,acc0,cc1,1
447
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
448
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
449
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
450
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
451
        test_accg_immed         0x00000011,accg0
452
        test_acc_immed  0x11111111,acc0
453
        test_accg_immed         0x00000022,accg1
454
        test_acc_immed  0x22222222,acc1
455
 
456
        set_fr_iimmed   1,2,fr7         ; multiply by 1
457
        set_fr_iimmed   2,1,fr8
458
        cmmachu         fr7,fr8,acc0,cc1,1
459
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
460
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
461
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
462
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
463
        test_accg_immed         0x00000011,accg0
464
        test_acc_immed  0x11111111,acc0
465
        test_accg_immed         0x00000022,accg1
466
        test_acc_immed  0x22222222,acc1
467
 
468
        set_fr_iimmed   0,2,fr7         ; multiply by 0
469
        set_fr_iimmed   2,0,fr8
470
        cmmachu         fr7,fr8,acc0,cc1,1
471
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
472
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
473
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
474
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
475
        test_accg_immed         0x00000011,accg0
476
        test_acc_immed  0x11111111,acc0
477
        test_accg_immed         0x00000022,accg1
478
        test_acc_immed  0x22222222,acc1
479
 
480
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
481
        set_fr_iimmed   2,0x3fff,fr8
482
        cmmachu         fr7,fr8,acc0,cc1,1
483
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
484
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
485
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
486
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
487
        test_accg_immed         0x00000011,accg0
488
        test_acc_immed  0x11111111,acc0
489
        test_accg_immed         0x00000022,accg1
490
        test_acc_immed  0x22222222,acc1
491
 
492
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
493
        set_fr_iimmed   2,0x4000,fr8
494
        cmmachu         fr7,fr8,acc0,cc1,1
495
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
496
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
497
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
498
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
499
        test_accg_immed         0x00000011,accg0
500
        test_acc_immed  0x11111111,acc0
501
        test_accg_immed         0x00000022,accg1
502
        test_acc_immed  0x22222222,acc1
503
 
504
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
505
        set_fr_iimmed   2,0x8000,fr8
506
        cmmachu         fr7,fr8,acc0,cc5,1
507
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
508
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
509
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
510
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
511
        test_accg_immed         0x00000011,accg0
512
        test_acc_immed  0x11111111,acc0
513
        test_accg_immed         0x00000022,accg1
514
        test_acc_immed  0x22222222,acc1
515
 
516
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
517
        set_fr_iimmed   0x7fff,0x7fff,fr8
518
        cmmachu         fr7,fr8,acc0,cc5,1
519
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
520
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
521
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
522
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
523
        test_accg_immed         0x00000011,accg0
524
        test_acc_immed  0x11111111,acc0
525
        test_accg_immed         0x00000022,accg1
526
        test_acc_immed  0x22222222,acc1
527
 
528
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
529
        set_fr_iimmed   0x8000,0x8000,fr8
530
        cmmachu         fr7,fr8,acc0,cc5,1
531
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
532
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
533
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
534
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
535
        test_accg_immed         0x00000011,accg0
536
        test_acc_immed  0x11111111,acc0
537
        test_accg_immed         0x00000022,accg1
538
        test_acc_immed  0x22222222,acc1
539
 
540
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
541
        set_fr_iimmed   0xffff,0xffff,fr8
542
        cmmachu         fr7,fr8,acc0,cc5,1
543
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
544
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
545
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
546
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
547
        test_accg_immed         0x00000011,accg0
548
        test_acc_immed  0x11111111,acc0
549
        test_accg_immed         0x00000022,accg1
550
        test_acc_immed  0x22222222,acc1
551
 
552
        set_accg_immed  0xff,accg0              ; saturation
553
        set_acc_immed   0xffffffff,acc0
554
        set_accg_immed  0xff,accg1
555
        set_acc_immed   0xffffffff,acc1
556
        set_fr_iimmed   1,1,fr7
557
        set_fr_iimmed   1,1,fr8
558
        cmmachu         fr7,fr8,acc0,cc5,1
559
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
560
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
561
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
562
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
563
        test_accg_immed         0xff,accg0              ; saturation
564
        test_acc_immed  0xffffffff,acc0
565
        test_accg_immed         0xff,accg1
566
        test_acc_immed  0xffffffff,acc1
567
 
568
        set_fr_iimmed   0xffff,0x0000,fr7
569
        set_fr_iimmed   0xffff,0xffff,fr8
570
        cmmachu         fr7,fr8,acc0,cc5,1
571
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
572
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
573
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
574
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
575
        test_accg_immed         0xff,accg0              ; saturation
576
        test_acc_immed  0xffffffff,acc0
577
        test_accg_immed         0xff,accg1
578
        test_acc_immed  0xffffffff,acc1
579
 
580
        set_spr_immed   0,msr0
581
        set_spr_immed   0,msr1
582
        set_accg_immed  0x00000011,accg0
583
        set_acc_immed   0x11111111,acc0
584
        set_accg_immed  0x00000022,accg1
585
        set_acc_immed   0x22222222,acc1
586
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
587
        set_fr_iimmed   2,3,fr8
588
        cmmachu         fr7,fr8,acc0,cc2,1
589
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
590
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
591
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
592
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
593
        test_accg_immed         0x00000011,accg0
594
        test_acc_immed  0x11111111,acc0
595
        test_accg_immed         0x00000022,accg1
596
        test_acc_immed  0x22222222,acc1
597
 
598
        set_fr_iimmed   1,2,fr7         ; multiply by 1
599
        set_fr_iimmed   2,1,fr8
600
        cmmachu         fr7,fr8,acc0,cc2,1
601
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
602
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
603
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
604
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
605
        test_accg_immed         0x00000011,accg0
606
        test_acc_immed  0x11111111,acc0
607
        test_accg_immed         0x00000022,accg1
608
        test_acc_immed  0x22222222,acc1
609
 
610
        set_fr_iimmed   0,2,fr7         ; multiply by 0
611
        set_fr_iimmed   2,0,fr8
612
        cmmachu         fr7,fr8,acc0,cc2,1
613
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
614
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
615
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
616
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
617
        test_accg_immed         0x00000011,accg0
618
        test_acc_immed  0x11111111,acc0
619
        test_accg_immed         0x00000022,accg1
620
        test_acc_immed  0x22222222,acc1
621
 
622
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
623
        set_fr_iimmed   2,0x3fff,fr8
624
        cmmachu         fr7,fr8,acc0,cc2,1
625
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
626
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
627
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
628
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
629
        test_accg_immed         0x00000011,accg0
630
        test_acc_immed  0x11111111,acc0
631
        test_accg_immed         0x00000022,accg1
632
        test_acc_immed  0x22222222,acc1
633
 
634
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
635
        set_fr_iimmed   2,0x4000,fr8
636
        cmmachu         fr7,fr8,acc0,cc2,1
637
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
638
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
639
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
640
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
641
        test_accg_immed         0x00000011,accg0
642
        test_acc_immed  0x11111111,acc0
643
        test_accg_immed         0x00000022,accg1
644
        test_acc_immed  0x22222222,acc1
645
 
646
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
647
        set_fr_iimmed   2,0x8000,fr8
648
        cmmachu         fr7,fr8,acc0,cc6,1
649
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
650
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
651
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
652
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
653
        test_accg_immed         0x00000011,accg0
654
        test_acc_immed  0x11111111,acc0
655
        test_accg_immed         0x00000022,accg1
656
        test_acc_immed  0x22222222,acc1
657
 
658
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
659
        set_fr_iimmed   0x7fff,0x7fff,fr8
660
        cmmachu         fr7,fr8,acc0,cc6,1
661
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
662
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
663
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
664
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
665
        test_accg_immed         0x00000011,accg0
666
        test_acc_immed  0x11111111,acc0
667
        test_accg_immed         0x00000022,accg1
668
        test_acc_immed  0x22222222,acc1
669
 
670
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
671
        set_fr_iimmed   0x8000,0x8000,fr8
672
        cmmachu         fr7,fr8,acc0,cc6,1
673
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
674
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
675
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
676
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
677
        test_accg_immed         0x00000011,accg0
678
        test_acc_immed  0x11111111,acc0
679
        test_accg_immed         0x00000022,accg1
680
        test_acc_immed  0x22222222,acc1
681
 
682
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
683
        set_fr_iimmed   0xffff,0xffff,fr8
684
        cmmachu         fr7,fr8,acc0,cc6,1
685
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
686
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
687
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
688
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
689
        test_accg_immed         0x00000011,accg0
690
        test_acc_immed  0x11111111,acc0
691
        test_accg_immed         0x00000022,accg1
692
        test_acc_immed  0x22222222,acc1
693
 
694
        set_accg_immed  0xff,accg0              ; saturation
695
        set_acc_immed   0xffffffff,acc0
696
        set_accg_immed  0xff,accg1
697
        set_acc_immed   0xffffffff,acc1
698
        set_fr_iimmed   1,1,fr7
699
        set_fr_iimmed   1,1,fr8
700
        cmmachu         fr7,fr8,acc0,cc6,1
701
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
702
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
703
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
704
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
705
        test_accg_immed         0xff,accg0              ; saturation
706
        test_acc_immed  0xffffffff,acc0
707
        test_accg_immed         0xff,accg1
708
        test_acc_immed  0xffffffff,acc1
709
 
710
        set_fr_iimmed   0xffff,0x0000,fr7
711
        set_fr_iimmed   0xffff,0xffff,fr8
712
        cmmachu         fr7,fr8,acc0,cc6,1
713
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
714
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
715
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
716
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
717
        test_accg_immed         0xff,accg0              ; saturation
718
        test_acc_immed  0xffffffff,acc0
719
        test_accg_immed         0xff,accg1
720
        test_acc_immed  0xffffffff,acc1
721
;
722
        set_spr_immed   0,msr0
723
        set_spr_immed   0,msr1
724
        set_accg_immed  0x00000011,accg0
725
        set_acc_immed   0x11111111,acc0
726
        set_accg_immed  0x00000022,accg1
727
        set_acc_immed   0x22222222,acc1
728
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
729
        set_fr_iimmed   2,3,fr8
730
        cmmachu         fr7,fr8,acc0,cc3,1
731
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
732
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
733
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
734
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
735
        test_accg_immed         0x00000011,accg0
736
        test_acc_immed  0x11111111,acc0
737
        test_accg_immed         0x00000022,accg1
738
        test_acc_immed  0x22222222,acc1
739
 
740
        set_fr_iimmed   1,2,fr7         ; multiply by 1
741
        set_fr_iimmed   2,1,fr8
742
        cmmachu         fr7,fr8,acc0,cc3,1
743
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
744
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
745
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
746
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
747
        test_accg_immed         0x00000011,accg0
748
        test_acc_immed  0x11111111,acc0
749
        test_accg_immed         0x00000022,accg1
750
        test_acc_immed  0x22222222,acc1
751
 
752
        set_fr_iimmed   0,2,fr7         ; multiply by 0
753
        set_fr_iimmed   2,0,fr8
754
        cmmachu         fr7,fr8,acc0,cc3,1
755
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
756
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
757
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
758
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
759
        test_accg_immed         0x00000011,accg0
760
        test_acc_immed  0x11111111,acc0
761
        test_accg_immed         0x00000022,accg1
762
        test_acc_immed  0x22222222,acc1
763
 
764
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
765
        set_fr_iimmed   2,0x3fff,fr8
766
        cmmachu         fr7,fr8,acc0,cc3,1
767
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
768
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
769
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
770
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
771
        test_accg_immed         0x00000011,accg0
772
        test_acc_immed  0x11111111,acc0
773
        test_accg_immed         0x00000022,accg1
774
        test_acc_immed  0x22222222,acc1
775
 
776
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
777
        set_fr_iimmed   2,0x4000,fr8
778
        cmmachu         fr7,fr8,acc0,cc3,1
779
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
780
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
781
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
782
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
783
        test_accg_immed         0x00000011,accg0
784
        test_acc_immed  0x11111111,acc0
785
        test_accg_immed         0x00000022,accg1
786
        test_acc_immed  0x22222222,acc1
787
 
788
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
789
        set_fr_iimmed   2,0x8000,fr8
790
        cmmachu         fr7,fr8,acc0,cc7,1
791
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
792
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
793
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
794
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
795
        test_accg_immed         0x00000011,accg0
796
        test_acc_immed  0x11111111,acc0
797
        test_accg_immed         0x00000022,accg1
798
        test_acc_immed  0x22222222,acc1
799
 
800
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
801
        set_fr_iimmed   0x7fff,0x7fff,fr8
802
        cmmachu         fr7,fr8,acc0,cc7,1
803
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
804
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
805
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
806
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
807
        test_accg_immed         0x00000011,accg0
808
        test_acc_immed  0x11111111,acc0
809
        test_accg_immed         0x00000022,accg1
810
        test_acc_immed  0x22222222,acc1
811
 
812
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
813
        set_fr_iimmed   0x8000,0x8000,fr8
814
        cmmachu         fr7,fr8,acc0,cc7,1
815
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
816
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
817
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
818
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
819
        test_accg_immed         0x00000011,accg0
820
        test_acc_immed  0x11111111,acc0
821
        test_accg_immed         0x00000022,accg1
822
        test_acc_immed  0x22222222,acc1
823
 
824
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
825
        set_fr_iimmed   0xffff,0xffff,fr8
826
        cmmachu         fr7,fr8,acc0,cc7,1
827
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
828
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
829
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
830
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
831
        test_accg_immed         0x00000011,accg0
832
        test_acc_immed  0x11111111,acc0
833
        test_accg_immed         0x00000022,accg1
834
        test_acc_immed  0x22222222,acc1
835
 
836
        set_accg_immed  0xff,accg0              ; saturation
837
        set_acc_immed   0xffffffff,acc0
838
        set_accg_immed  0xff,accg1
839
        set_acc_immed   0xffffffff,acc1
840
        set_fr_iimmed   1,1,fr7
841
        set_fr_iimmed   1,1,fr8
842
        cmmachu         fr7,fr8,acc0,cc7,1
843
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
844
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
845
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
846
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
847
        test_accg_immed         0xff,accg0              ; saturation
848
        test_acc_immed  0xffffffff,acc0
849
        test_accg_immed         0xff,accg1
850
        test_acc_immed  0xffffffff,acc1
851
 
852
        set_fr_iimmed   0xffff,0x0000,fr7
853
        set_fr_iimmed   0xffff,0xffff,fr8
854
        cmmachu         fr7,fr8,acc0,cc7,1
855
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
856
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
857
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
858
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
859
        test_accg_immed         0xff,accg0              ; saturation
860
        test_acc_immed  0xffffffff,acc0
861
        test_accg_immed         0xff,accg1
862
        test_acc_immed  0xffffffff,acc1
863
 
864
        pass

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