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jeremybenn |
# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond
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# mach: all
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.include "testutils.inc"
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start
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.global csdiv
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csdiv:
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set_spr_immed 0x1b1b,cccr
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc4,1
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test_gr_immed 4,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc4,1
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test_gr_immed -1,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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; set up exception handler
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set_psr_et 1
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x170,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_gr_immed 0,gr15
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; divide will cause overflow
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set_spr_addr ok1,lr
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set_gr_addr e1,gr17
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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e1: csdiv gr1,gr3,gr2,cc4,1
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test_gr_immed 1,gr15
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test_gr_limmed 0x8000,0x0000,gr2
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; Special case from the Arch Spec Vol 2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc4,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc4,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc4,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc4,0
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test_gr_limmed 0x7fff,0xffff,gr2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc4,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc5,0
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test_gr_immed 4,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc5,0
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test_gr_immed -1,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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; divide will cause overflow
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set_spr_addr ok1,lr
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set_gr_addr e2,gr17
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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e2: csdiv gr1,gr3,gr2,cc5,0
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test_gr_immed 2,gr15
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test_gr_limmed 0x8000,0x0000,gr2
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; Special case from the Arch Spec Vol 2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc5,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc5,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc5,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc5,1
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test_gr_limmed 0x7fff,0xffff,gr2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc5,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc6,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc6,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc6,0
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test_gr_limmed 0x7fff,0xffff,gr2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc6,0
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test_gr_limmed 0x7fff,0xffff,gr2
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; simple division 12 / 3
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set_gr_immed 3,gr3
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set_gr_immed 12,gr1
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csdiv gr1,gr3,gr2,cc7,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; Random example
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set_gr_limmed 0x0123,0x4567,gr3
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set_gr_limmed 0xfedc,0xba98,gr1
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csdiv gr1,gr3,gr2,cc7,1
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test_gr_limmed 0x7fff,0xffff,gr2
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; Special case from the Arch Spec Vol 2
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and_spr_immed -33,isr ; turn off isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc7,1
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test_gr_limmed 0x7fff,0xffff,gr2
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or_spr_immed 0x20,isr ; turn on isr.edem
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set_gr_immed -1,gr3
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set_gr_limmed 0x8000,0x0000,gr1
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csdiv gr1,gr3,gr2,cc7,1
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test_gr_limmed 0x7fff,0xffff,gr2
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pass
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ok1: ; exception handler for overflow
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test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set
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test_spr_gr epcr0,gr17 ; return address set
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
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inc_gr_immed 1,gr15
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rett 0
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fail
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