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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [fcbeqlr.cgs] - Blame information for rev 842

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# frv testcase for fcbeqlr $FCCi,$ccond,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fcbeqlr
fcbeqlr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbeqlr         fcc0,0,0
 
        set_spr_addr    bad,lr
        set_fcc         0x1 1
        fcbeqlr         fcc1,0,1
 
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbeqlr         fcc2,0,2
 
        set_spr_addr    bad,lr
        set_fcc         0x3 3
        fcbeqlr         fcc3,0,3
 
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        fcbeqlr         fcc0,0,0
 
        set_spr_addr    bad,lr
        set_fcc         0x5 1
        fcbeqlr         fcc1,0,1
 
        set_spr_addr    bad,lr
        set_fcc         0x6 2
        fcbeqlr         fcc2,0,2
 
        set_spr_addr    bad,lr
        set_fcc         0x7 3
        fcbeqlr         fcc3,0,3
 
        set_spr_addr    ok9,lr
        set_fcc         0x8 0
        fcbeqlr         fcc0,0,0
        fail
ok9:
        set_spr_addr    oka,lr
        set_fcc         0x9 1
        fcbeqlr         fcc1,0,1
        fail
oka:
        set_spr_addr    okb,lr
        set_fcc         0xa 2
        fcbeqlr         fcc2,0,2
        fail
okb:
        set_spr_addr    okc,lr
        set_fcc         0xb 3
        fcbeqlr         fcc3,0,3
        fail
okc:
        set_spr_addr    okd,lr
        set_fcc         0xc 0
        fcbeqlr         fcc0,0,0
        fail
okd:
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        fcbeqlr         fcc1,0,1
        fail
oke:
        set_spr_addr    okf,lr
        set_fcc         0xe 2
        fcbeqlr         fcc2,0,2
        fail
okf:
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        fcbeqlr         fcc3,0,3
        fail
okg:
 
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbeqlr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x1 1
        fcbeqlr         fcc1,1,1
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbeqlr         fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x3 3
        fcbeqlr         fcc3,1,3
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        fcbeqlr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x5 1
        fcbeqlr         fcc1,1,1
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x6 2
        fcbeqlr         fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x7 3
        fcbeqlr         fcc3,1,3
 
        set_spr_immed   1,lcr
        set_spr_addr    okp,lr
        set_fcc         0x8 0
        fcbeqlr         fcc0,1,0
        fail
okp:
        set_spr_immed   1,lcr
        set_spr_addr    okq,lr
        set_fcc         0x9 1
        fcbeqlr         fcc1,1,1
        fail
okq:
        set_spr_immed   1,lcr
        set_spr_addr    okr,lr
        set_fcc         0xa 2
        fcbeqlr         fcc2,1,2
        fail
okr:
        set_spr_immed   1,lcr
        set_spr_addr    oks,lr
        set_fcc         0xb 3
        fcbeqlr         fcc3,1,3
        fail
oks:
        set_spr_immed   1,lcr
        set_spr_addr    okt,lr
        set_fcc         0xc 0
        fcbeqlr         fcc0,1,0
        fail
okt:
        set_spr_immed   1,lcr
        set_spr_addr    oku,lr
        set_fcc         0xd 1
        fcbeqlr         fcc1,1,1
        fail
oku:
        set_spr_immed   1,lcr
        set_spr_addr    okv,lr
        set_fcc         0xe 2
        fcbeqlr         fcc2,1,2
        fail
okv:
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_fcc         0xf 3
        fcbeqlr         fcc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
 
        set_fcc         0x0 0
        fcbeqlr fcc0,1,0
        set_fcc         0x1 1
        fcbeqlr fcc1,1,1
        set_fcc         0x2 2
        fcbeqlr fcc2,1,2
        set_fcc         0x3 3
        fcbeqlr fcc3,1,3
        set_fcc         0x4 0
        fcbeqlr fcc0,1,0
        set_fcc         0x5 1
        fcbeqlr fcc1,1,1
        set_fcc         0x6 2
        fcbeqlr fcc2,1,2
        set_fcc         0x7 3
        fcbeqlr fcc3,1,3
        set_fcc         0x8 0
        fcbeqlr fcc0,1,0
        set_fcc         0x9 1
        fcbeqlr fcc1,1,1
        set_fcc         0xa 2
        fcbeqlr fcc2,1,2
        set_fcc         0xb 3
        fcbeqlr fcc3,1,3
        set_fcc         0xc 0
        fcbeqlr fcc0,1,0
        set_fcc         0xd 1
        fcbeqlr fcc1,1,1
        set_fcc         0xe 2
        fcbeqlr fcc2,1,2
        set_fcc         0xf 3
        fcbeqlr fcc3,1,3
 
        ; ccond is false
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        fcbeqlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        fcbeqlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        fcbeqlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        fcbeqlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        fcbeqlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        fcbeqlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        fcbeqlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        fcbeqlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        fcbeqlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        fcbeqlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        fcbeqlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        fcbeqlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        fcbeqlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        fcbeqlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        fcbeqlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        fcbeqlr fcc3,0,3
 
        pass
bad:
        fail

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [fcbeqlr.cgs] - Blame information for rev 842

Line No.	Rev	Author	Line
1	227	jeremybenn	`# frv testcase for fcbeqlr $FCCi,$ccond,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fcbeqlr`
9			`fcbeqlr:`
10			`; ccond is true`
11			`set_spr_immed 128,lcr`
12			`set_spr_addr bad,lr`
13			`set_fcc 0x0 0`
14			`fcbeqlr fcc0,0,0`
15
16			`set_spr_addr bad,lr`
17			`set_fcc 0x1 1`
18			`fcbeqlr fcc1,0,1`
19
20			`set_spr_addr bad,lr`
21			`set_fcc 0x2 2`
22			`fcbeqlr fcc2,0,2`
23
24			`set_spr_addr bad,lr`
25			`set_fcc 0x3 3`
26			`fcbeqlr fcc3,0,3`
27
28			`set_spr_addr bad,lr`
29			`set_fcc 0x4 0`
30			`fcbeqlr fcc0,0,0`
31
32			`set_spr_addr bad,lr`
33			`set_fcc 0x5 1`
34			`fcbeqlr fcc1,0,1`
35
36			`set_spr_addr bad,lr`
37			`set_fcc 0x6 2`
38			`fcbeqlr fcc2,0,2`
39
40			`set_spr_addr bad,lr`
41			`set_fcc 0x7 3`
42			`fcbeqlr fcc3,0,3`
43
44			`set_spr_addr ok9,lr`
45			`set_fcc 0x8 0`
46			`fcbeqlr fcc0,0,0`
47			`fail`
48			`ok9:`
49			`set_spr_addr oka,lr`
50			`set_fcc 0x9 1`
51			`fcbeqlr fcc1,0,1`
52			`fail`
53			`oka:`
54			`set_spr_addr okb,lr`
55			`set_fcc 0xa 2`
56			`fcbeqlr fcc2,0,2`
57			`fail`
58			`okb:`
59			`set_spr_addr okc,lr`
60			`set_fcc 0xb 3`
61			`fcbeqlr fcc3,0,3`
62			`fail`
63			`okc:`
64			`set_spr_addr okd,lr`
65			`set_fcc 0xc 0`
66			`fcbeqlr fcc0,0,0`
67			`fail`
68			`okd:`
69			`set_spr_addr oke,lr`
70			`set_fcc 0xd 1`
71			`fcbeqlr fcc1,0,1`
72			`fail`
73			`oke:`
74			`set_spr_addr okf,lr`
75			`set_fcc 0xe 2`
76			`fcbeqlr fcc2,0,2`
77			`fail`
78			`okf:`
79			`set_spr_addr okg,lr`
80			`set_fcc 0xf 3`
81			`fcbeqlr fcc3,0,3`
82			`fail`
83			`okg:`
84
85			`; ccond is true`
86			`set_spr_immed 1,lcr`
87			`set_spr_addr bad,lr`
88			`set_fcc 0x0 0`
89			`fcbeqlr fcc0,1,0`
90
91			`set_spr_immed 1,lcr`
92			`set_spr_addr bad,lr`
93			`set_fcc 0x1 1`
94			`fcbeqlr fcc1,1,1`
95
96			`set_spr_immed 1,lcr`
97			`set_spr_addr bad,lr`
98			`set_fcc 0x2 2`
99			`fcbeqlr fcc2,1,2`
100
101			`set_spr_immed 1,lcr`
102			`set_spr_addr bad,lr`
103			`set_fcc 0x3 3`
104			`fcbeqlr fcc3,1,3`
105
106			`set_spr_immed 1,lcr`
107			`set_spr_addr bad,lr`
108			`set_fcc 0x4 0`
109			`fcbeqlr fcc0,1,0`
110
111			`set_spr_immed 1,lcr`
112			`set_spr_addr bad,lr`
113			`set_fcc 0x5 1`
114			`fcbeqlr fcc1,1,1`
115
116			`set_spr_immed 1,lcr`
117			`set_spr_addr bad,lr`
118			`set_fcc 0x6 2`
119			`fcbeqlr fcc2,1,2`
120
121			`set_spr_immed 1,lcr`
122			`set_spr_addr bad,lr`
123			`set_fcc 0x7 3`
124			`fcbeqlr fcc3,1,3`
125
126			`set_spr_immed 1,lcr`
127			`set_spr_addr okp,lr`
128			`set_fcc 0x8 0`
129			`fcbeqlr fcc0,1,0`
130			`fail`
131			`okp:`
132			`set_spr_immed 1,lcr`
133			`set_spr_addr okq,lr`
134			`set_fcc 0x9 1`
135			`fcbeqlr fcc1,1,1`
136			`fail`
137			`okq:`
138			`set_spr_immed 1,lcr`
139			`set_spr_addr okr,lr`
140			`set_fcc 0xa 2`
141			`fcbeqlr fcc2,1,2`
142			`fail`
143			`okr:`
144			`set_spr_immed 1,lcr`
145			`set_spr_addr oks,lr`
146			`set_fcc 0xb 3`
147			`fcbeqlr fcc3,1,3`
148			`fail`
149			`oks:`
150			`set_spr_immed 1,lcr`
151			`set_spr_addr okt,lr`
152			`set_fcc 0xc 0`
153			`fcbeqlr fcc0,1,0`
154			`fail`
155			`okt:`
156			`set_spr_immed 1,lcr`
157			`set_spr_addr oku,lr`
158			`set_fcc 0xd 1`
159			`fcbeqlr fcc1,1,1`
160			`fail`
161			`oku:`
162			`set_spr_immed 1,lcr`
163			`set_spr_addr okv,lr`
164			`set_fcc 0xe 2`
165			`fcbeqlr fcc2,1,2`
166			`fail`
167			`okv:`
168			`set_spr_immed 1,lcr`
169			`set_spr_addr okw,lr`
170			`set_fcc 0xf 3`
171			`fcbeqlr fcc3,1,3`
172			`fail`
173			`okw:`
174			`; ccond is false`
175			`set_spr_immed 128,lcr`
176
177			`set_fcc 0x0 0`
178			`fcbeqlr fcc0,1,0`
179			`set_fcc 0x1 1`
180			`fcbeqlr fcc1,1,1`
181			`set_fcc 0x2 2`
182			`fcbeqlr fcc2,1,2`
183			`set_fcc 0x3 3`
184			`fcbeqlr fcc3,1,3`
185			`set_fcc 0x4 0`
186			`fcbeqlr fcc0,1,0`
187			`set_fcc 0x5 1`
188			`fcbeqlr fcc1,1,1`
189			`set_fcc 0x6 2`
190			`fcbeqlr fcc2,1,2`
191			`set_fcc 0x7 3`
192			`fcbeqlr fcc3,1,3`
193			`set_fcc 0x8 0`
194			`fcbeqlr fcc0,1,0`
195			`set_fcc 0x9 1`
196			`fcbeqlr fcc1,1,1`
197			`set_fcc 0xa 2`
198			`fcbeqlr fcc2,1,2`
199			`set_fcc 0xb 3`
200			`fcbeqlr fcc3,1,3`
201			`set_fcc 0xc 0`
202			`fcbeqlr fcc0,1,0`
203			`set_fcc 0xd 1`
204			`fcbeqlr fcc1,1,1`
205			`set_fcc 0xe 2`
206			`fcbeqlr fcc2,1,2`
207			`set_fcc 0xf 3`
208			`fcbeqlr fcc3,1,3`
209
210			`; ccond is false`
211			`set_spr_immed 1,lcr`
212			`set_fcc 0x0 0`
213			`fcbeqlr fcc0,0,0`
214			`set_spr_immed 1,lcr`
215			`set_fcc 0x1 1`
216			`fcbeqlr fcc1,0,1`
217			`set_spr_immed 1,lcr`
218			`set_fcc 0x2 2`
219			`fcbeqlr fcc2,0,2`
220			`set_spr_immed 1,lcr`
221			`set_fcc 0x3 3`
222			`fcbeqlr fcc3,0,3`
223			`set_spr_immed 1,lcr`
224			`set_fcc 0x4 0`
225			`fcbeqlr fcc0,0,0`
226			`set_spr_immed 1,lcr`
227			`set_fcc 0x5 1`
228			`fcbeqlr fcc1,0,1`
229			`set_spr_immed 1,lcr`
230			`set_fcc 0x6 2`
231			`fcbeqlr fcc2,0,2`
232			`set_spr_immed 1,lcr`
233			`set_fcc 0x7 3`
234			`fcbeqlr fcc3,0,3`
235			`set_spr_immed 1,lcr`
236			`set_fcc 0x8 0`
237			`fcbeqlr fcc0,0,0`
238			`set_spr_immed 1,lcr`
239			`set_fcc 0x9 1`
240			`fcbeqlr fcc1,0,1`
241			`set_spr_immed 1,lcr`
242			`set_fcc 0xa 2`
243			`fcbeqlr fcc2,0,2`
244			`set_spr_immed 1,lcr`
245			`set_fcc 0xb 3`
246			`fcbeqlr fcc3,0,3`
247			`set_spr_immed 1,lcr`
248			`set_fcc 0xc 0`
249			`fcbeqlr fcc0,0,0`
250			`set_spr_immed 1,lcr`
251			`set_fcc 0xd 1`
252			`fcbeqlr fcc1,0,1`
253			`set_spr_immed 1,lcr`
254			`set_fcc 0xe 2`
255			`fcbeqlr fcc2,0,2`
256			`set_spr_immed 1,lcr`
257			`set_fcc 0xf 3`
258			`fcbeqlr fcc3,0,3`
259
260			`pass`
261			`bad:`
262			`fail`