OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [masaccs.cgs] - Blame information for rev 834

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
# frv testcase for masaccs $ACC40Si,$ACC40Sk
2 
# mach: fr400
3 
 
4 
        .include "../testutils.inc"
5 
 
6 
        start
7 
 
8 
        .global masaccs
9 
masaccs:
10 
        set_accg_immed  0,accg0
11 
        set_acc_immed   0x00000000,acc0
12 
        set_accg_immed  0,accg1
13 
        set_acc_immed   0x00000000,acc1
14 
        masaccs         acc0,acc2
15 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
16 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
17 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
18 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
19 
        test_accg_immed 0,accg2
20 
        test_acc_limmed 0x0000,0x0000,acc2
21 
        test_accg_immed 0,accg3
22 
        test_acc_limmed 0x0000,0x0000,acc3
23 
 
24 
        set_accg_immed  0,accg0
25 
        set_acc_immed   0xdead0000,acc0
26 
        set_accg_immed  0,accg1
27 
        set_acc_immed   0x0000beef,acc1
28 
        masaccs         acc0,acc2
29 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
30 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
31 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
32 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
33 
        test_accg_immed 0,accg2
34 
        test_acc_limmed 0xdead,0xbeef,acc2
35 
        test_accg_immed 0,accg3
36 
        test_acc_limmed 0xdeac,0x4111,acc3
37 
 
38 
        set_accg_immed  0,accg0
39 
        set_acc_immed   0x0000dead,acc0
40 
        set_accg_immed  0,accg1
41 
        set_acc_immed   0xbeef0000,acc1
42 
        masaccs         acc0,acc2
43 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
44 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
45 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
46 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
47 
        test_accg_immed 0,accg2
48 
        test_acc_limmed 0xbeef,0xdead,acc2
49 
        test_accg_immed 0xff,accg3
50 
        test_acc_limmed 0x4111,0xdead,acc3
51 
 
52 
        set_accg_immed  0,accg0
53 
        set_acc_immed   0x12345678,acc0
54 
        set_accg_immed  0,accg1
55 
        set_acc_immed   0x11111111,acc1
56 
        masaccs         acc0,acc2
57 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
58 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
59 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
60 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
61 
        test_accg_immed 0,accg2
62 
        test_acc_limmed 0x2345,0x6789,acc2
63 
        test_accg_immed 0,accg3
64 
        test_acc_limmed 0x0123,0x4567,acc3
65 
 
66 
        set_accg_immed  0,accg0
67 
        set_acc_immed   0x12345678,acc0
68 
        set_accg_immed  0,accg1
69 
        set_acc_immed   0xffffffff,acc1
70 
        masaccs         acc0,acc2
71 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
72 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
73 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
74 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
75 
        test_accg_immed 1,accg2
76 
        test_acc_limmed 0x1234,0x5677,acc2
77 
        test_accg_immed 0xff,accg3
78 
        test_acc_limmed 0x1234,0x5679,acc3
79 
 
80 
        set_accg_immed  0,accg0
81 
        set_acc_immed   0x12345678,acc0
82 
        set_accg_immed  0xff,accg1
83 
        set_acc_immed   0xffffffff,acc1
84 
        masaccs         acc0,acc2
85 
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
86 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
87 
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
88 
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
89 
        test_accg_immed 0,accg2
90 
        test_acc_limmed 0x1234,0x5677,acc2
91 
        test_accg_immed 0,accg3
92 
        test_acc_limmed 0x1234,0x5679,acc3
93 
 
94 
        set_spr_immed   0,msr0
95 
        set_accg_immed  0x7f,accg0
96 
        set_acc_immed   0xfffe7ffe,acc0
97 
        set_accg_immed  0x0,accg1
98 
        set_acc_immed   0x00020001,acc1
99 
        masaccs         acc0,acc2
100 
        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
101 
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
102 
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
103 
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
104 
        test_accg_immed 0x7f,accg2
105 
        test_acc_limmed 0xffff,0xffff,acc2
106 
        test_accg_immed 0x7f,accg3
107 
        test_acc_limmed 0xfffc,0x7ffd,acc3
108 
 
109 
        set_spr_immed   0,msr0
110 
        set_accg_immed  0x80,accg0
111 
        set_acc_immed   0x00000001,acc0
112 
        set_accg_immed  0xff,accg1
113 
        set_acc_immed   0xfffffffe,acc1
114 
        masaccs         acc0,acc2
115 
        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
116 
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
117 
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
118 
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
119 
        test_accg_immed 0x80,accg2
120 
        test_acc_limmed 0x0000,0x0000,acc2
121 
        test_accg_immed 0x80,accg3
122 
        test_acc_limmed 0x0000,0x0003,acc3
123 
 
124 
        set_spr_immed   0,msr0
125 
        set_spr_immed   0,msr1
126 
        set_accg_immed  0,accg0
127 
        set_acc_immed   0x00000001,acc0
128 
        set_accg_immed  0,accg1
129 
        set_acc_immed   0x00000001,acc1
130 
        set_accg_immed  0,accg2
131 
        set_acc_immed   0x00000001,acc2
132 
        set_accg_immed  0x7f,accg3
133 
        set_acc_immed   0xffffffff,acc3
134 
        masaccs.p       acc0,acc0
135 
        masaccs         acc2,acc2
136 
        test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie not set
137 
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
138 
        test_spr_bits   0x3c,2,0x8,msr1         ; msr1.sie is set
139 
        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
140 
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
141 
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
142 
        test_accg_immed 0,accg0
143 
        test_acc_limmed 0x0000,0x0002,acc0
144 
        test_accg_immed 0,accg1
145 
        test_acc_limmed 0x0000,0x0000,acc1
146 
        test_accg_immed 0x7f,accg2
147 
        test_acc_limmed 0xffff,0xffff,acc2
148 
        test_accg_immed 0x80,accg3
149 
        test_acc_limmed 0x0000,0x0002,acc3
150 
 
151 
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.