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jeremybenn |
# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
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# mach: all
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.include "../testutils.inc"
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start
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.global cmqaddhus
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cmqaddhus:
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set_spr_immed 0x1b1b,cccr
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0xdead,0x0000,fr11
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set_fr_iimmed 0x0000,0x0000,fr12
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set_fr_iimmed 0x0000,0xbeef,fr13
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cmqaddhus fr10,fr12,fr14,cc0,1
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0xdead,0xbeef,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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set_fr_iimmed 0xbeef,0x0000,fr12
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set_fr_iimmed 0x1111,0x1111,fr13
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cmqaddhus fr10,fr12,fr14,cc0,1
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test_fr_limmed 0xbeef,0xdead,fr14
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test_fr_limmed 0x2345,0x6789,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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set_fr_iimmed 0x0002,0x0001,fr12
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set_fr_iimmed 0x0001,0x0002,fr13
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cmqaddhus fr10,fr12,fr14,cc4,1
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test_fr_limmed 0x8000,0x7fff,fr14
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test_fr_limmed 0xffff,0xffff,fr15
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test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0002,0x0001,fr10
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set_fr_iimmed 0x0001,0x0001,fr11
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set_fr_iimmed 0xfffe,0xfffe,fr12
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set_fr_iimmed 0x8000,0x8000,fr13
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cmqaddhus.p fr10,fr10,fr14,cc4,1
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cmqaddhus fr12,fr12,fr16,cc4,1
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test_fr_limmed 0x0004,0x0002,fr14
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test_fr_limmed 0x0002,0x0002,fr15
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test_fr_limmed 0xffff,0xffff,fr16
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test_fr_limmed 0xffff,0xffff,fr17
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test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0xdead,0x0000,fr11
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set_fr_iimmed 0x0000,0x0000,fr12
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set_fr_iimmed 0x0000,0xbeef,fr13
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cmqaddhus fr10,fr12,fr14,cc1,0
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0xdead,0xbeef,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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set_fr_iimmed 0xbeef,0x0000,fr12
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set_fr_iimmed 0x1111,0x1111,fr13
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cmqaddhus fr10,fr12,fr14,cc1,0
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test_fr_limmed 0xbeef,0xdead,fr14
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test_fr_limmed 0x2345,0x6789,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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set_fr_iimmed 0x0002,0x0001,fr12
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set_fr_iimmed 0x0001,0x0002,fr13
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cmqaddhus fr10,fr12,fr14,cc5,0
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test_fr_limmed 0x8000,0x7fff,fr14
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test_fr_limmed 0xffff,0xffff,fr15
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test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0002,0x0001,fr10
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set_fr_iimmed 0x0001,0x0001,fr11
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set_fr_iimmed 0xfffe,0xfffe,fr12
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set_fr_iimmed 0x8000,0x8000,fr13
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cmqaddhus.p fr10,fr10,fr14,cc5,0
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cmqaddhus fr12,fr12,fr16,cc5,0
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test_fr_limmed 0x0004,0x0002,fr14
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test_fr_limmed 0x0002,0x0002,fr15
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test_fr_limmed 0xffff,0xffff,fr16
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test_fr_limmed 0xffff,0xffff,fr17
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test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_fr_iimmed 0x1111,0x1111,fr14
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set_fr_iimmed 0x2222,0x2222,fr15
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0xdead,0x0000,fr11
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set_fr_iimmed 0x0000,0x0000,fr12
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set_fr_iimmed 0x0000,0xbeef,fr13
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cmqaddhus fr10,fr12,fr14,cc0,0
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test_fr_limmed 0x1111,0x1111,fr14
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test_fr_limmed 0x2222,0x2222,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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set_fr_iimmed 0xbeef,0x0000,fr12
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set_fr_iimmed 0x1111,0x1111,fr13
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cmqaddhus fr10,fr12,fr14,cc0,0
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test_fr_limmed 0x1111,0x1111,fr14
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test_fr_limmed 0x2222,0x2222,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 142 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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set_fr_iimmed 0x0002,0x0001,fr12
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| 147 |
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set_fr_iimmed 0x0001,0x0002,fr13
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| 148 |
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cmqaddhus fr10,fr12,fr14,cc4,0
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| 149 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 150 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 151 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 152 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 153 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 154 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 155 |
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| 156 |
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set_fr_iimmed 0x3333,0x3333,fr16
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| 157 |
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set_fr_iimmed 0x4444,0x4444,fr17
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| 158 |
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set_spr_immed 0,msr0
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| 159 |
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set_fr_iimmed 0x0002,0x0001,fr10
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| 160 |
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set_fr_iimmed 0x0001,0x0001,fr11
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| 161 |
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set_fr_iimmed 0xfffe,0xfffe,fr12
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| 162 |
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set_fr_iimmed 0x8000,0x8000,fr13
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cmqaddhus.p fr10,fr10,fr14,cc4,0
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| 164 |
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cmqaddhus fr12,fr12,fr16,cc4,0
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| 165 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 166 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 167 |
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test_fr_limmed 0x3333,0x3333,fr16
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| 168 |
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test_fr_limmed 0x4444,0x4444,fr17
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| 169 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 170 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 171 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 172 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 173 |
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| 174 |
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set_fr_iimmed 0x1111,0x1111,fr14
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| 175 |
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set_fr_iimmed 0x2222,0x2222,fr15
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| 176 |
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set_spr_immed 0,msr0
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| 177 |
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set_fr_iimmed 0x0000,0x0000,fr10
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| 178 |
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set_fr_iimmed 0xdead,0x0000,fr11
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| 179 |
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set_fr_iimmed 0x0000,0x0000,fr12
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| 180 |
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set_fr_iimmed 0x0000,0xbeef,fr13
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| 181 |
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cmqaddhus fr10,fr12,fr14,cc1,1
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| 182 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 183 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 184 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 185 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 186 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 187 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 188 |
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| 189 |
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set_fr_iimmed 0x0000,0xdead,fr10
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| 190 |
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set_fr_iimmed 0x1234,0x5678,fr11
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| 191 |
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set_fr_iimmed 0xbeef,0x0000,fr12
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| 192 |
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set_fr_iimmed 0x1111,0x1111,fr13
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| 193 |
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cmqaddhus fr10,fr12,fr14,cc1,1
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| 194 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 195 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 196 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 197 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 198 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 199 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 200 |
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| 201 |
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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| 202 |
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set_fr_iimmed 0xfffe,0xfffe,fr11
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| 203 |
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set_fr_iimmed 0x0002,0x0001,fr12
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| 204 |
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set_fr_iimmed 0x0001,0x0002,fr13
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| 205 |
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cmqaddhus fr10,fr12,fr14,cc5,1
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| 206 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 207 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 208 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 209 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 210 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 211 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 212 |
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| 213 |
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set_fr_iimmed 0x3333,0x3333,fr16
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| 214 |
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set_fr_iimmed 0x4444,0x4444,fr17
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| 215 |
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set_spr_immed 0,msr0
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| 216 |
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set_fr_iimmed 0x0002,0x0001,fr10
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| 217 |
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set_fr_iimmed 0x0001,0x0001,fr11
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| 218 |
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set_fr_iimmed 0xfffe,0xfffe,fr12
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| 219 |
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set_fr_iimmed 0x8000,0x8000,fr13
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| 220 |
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cmqaddhus.p fr10,fr10,fr14,cc5,1
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| 221 |
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cmqaddhus fr12,fr12,fr16,cc5,1
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| 222 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 223 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 224 |
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test_fr_limmed 0x3333,0x3333,fr16
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| 225 |
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test_fr_limmed 0x4444,0x4444,fr17
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| 226 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 227 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 228 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 229 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 230 |
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| 231 |
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set_fr_iimmed 0x1111,0x1111,fr14
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| 232 |
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set_fr_iimmed 0x2222,0x2222,fr15
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| 233 |
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set_spr_immed 0,msr0
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| 234 |
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set_fr_iimmed 0x0000,0x0000,fr10
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| 235 |
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set_fr_iimmed 0xdead,0x0000,fr11
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| 236 |
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set_fr_iimmed 0x0000,0x0000,fr12
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| 237 |
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set_fr_iimmed 0x0000,0xbeef,fr13
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| 238 |
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cmqaddhus fr10,fr12,fr14,cc2,1
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| 239 |
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test_fr_limmed 0x1111,0x1111,fr14
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| 240 |
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test_fr_limmed 0x2222,0x2222,fr15
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| 241 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 242 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 243 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 244 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 245 |
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| 246 |
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set_fr_iimmed 0x0000,0xdead,fr10
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| 247 |
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set_fr_iimmed 0x1234,0x5678,fr11
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| 248 |
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set_fr_iimmed 0xbeef,0x0000,fr12
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| 249 |
|
|
set_fr_iimmed 0x1111,0x1111,fr13
|
| 250 |
|
|
cmqaddhus fr10,fr12,fr14,cc2,0
|
| 251 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 252 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 253 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 254 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 255 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 256 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 257 |
|
|
|
| 258 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
| 259 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
| 260 |
|
|
set_fr_iimmed 0x0002,0x0001,fr12
|
| 261 |
|
|
set_fr_iimmed 0x0001,0x0002,fr13
|
| 262 |
|
|
cmqaddhus fr10,fr12,fr14,cc6,1
|
| 263 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 264 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 265 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 266 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 267 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 268 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 269 |
|
|
|
| 270 |
|
|
set_fr_iimmed 0x3333,0x3333,fr16
|
| 271 |
|
|
set_fr_iimmed 0x4444,0x4444,fr17
|
| 272 |
|
|
set_spr_immed 0,msr0
|
| 273 |
|
|
set_fr_iimmed 0x0002,0x0001,fr10
|
| 274 |
|
|
set_fr_iimmed 0x0001,0x0001,fr11
|
| 275 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr12
|
| 276 |
|
|
set_fr_iimmed 0x8000,0x8000,fr13
|
| 277 |
|
|
cmqaddhus.p fr10,fr10,fr14,cc6,0
|
| 278 |
|
|
cmqaddhus fr12,fr12,fr16,cc6,1
|
| 279 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 280 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 281 |
|
|
test_fr_limmed 0x3333,0x3333,fr16
|
| 282 |
|
|
test_fr_limmed 0x4444,0x4444,fr17
|
| 283 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 284 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 285 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 286 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 287 |
|
|
|
| 288 |
|
|
set_fr_iimmed 0x1111,0x1111,fr14
|
| 289 |
|
|
set_fr_iimmed 0x2222,0x2222,fr15
|
| 290 |
|
|
set_spr_immed 0,msr0
|
| 291 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
| 292 |
|
|
set_fr_iimmed 0xdead,0x0000,fr11
|
| 293 |
|
|
set_fr_iimmed 0x0000,0x0000,fr12
|
| 294 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr13
|
| 295 |
|
|
cmqaddhus fr10,fr12,fr14,cc3,1
|
| 296 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 297 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 298 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 299 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 300 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 301 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 302 |
|
|
|
| 303 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
| 304 |
|
|
set_fr_iimmed 0x1234,0x5678,fr11
|
| 305 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr12
|
| 306 |
|
|
set_fr_iimmed 0x1111,0x1111,fr13
|
| 307 |
|
|
cmqaddhus fr10,fr12,fr14,cc3,0
|
| 308 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 309 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 310 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 311 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 312 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 313 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 314 |
|
|
|
| 315 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
| 316 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
| 317 |
|
|
set_fr_iimmed 0x0002,0x0001,fr12
|
| 318 |
|
|
set_fr_iimmed 0x0001,0x0002,fr13
|
| 319 |
|
|
cmqaddhus fr10,fr12,fr14,cc7,1
|
| 320 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 321 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 322 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 323 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 324 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 325 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 326 |
|
|
|
| 327 |
|
|
set_fr_iimmed 0x3333,0x3333,fr16
|
| 328 |
|
|
set_fr_iimmed 0x4444,0x4444,fr17
|
| 329 |
|
|
set_spr_immed 0,msr0
|
| 330 |
|
|
set_fr_iimmed 0x0002,0x0001,fr10
|
| 331 |
|
|
set_fr_iimmed 0x0001,0x0001,fr11
|
| 332 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr12
|
| 333 |
|
|
set_fr_iimmed 0x8000,0x8000,fr13
|
| 334 |
|
|
cmqaddhus.p fr10,fr10,fr14,cc7,0
|
| 335 |
|
|
cmqaddhus fr12,fr12,fr16,cc7,1
|
| 336 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
| 337 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
| 338 |
|
|
test_fr_limmed 0x3333,0x3333,fr16
|
| 339 |
|
|
test_fr_limmed 0x4444,0x4444,fr17
|
| 340 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 341 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 342 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 343 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 344 |
|
|
|
| 345 |
|
|
pass
|
