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jeremybenn |
# frv testcase for mqmachu $GRi,$GRj,$GRk
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# mach: all
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.include "../testutils.inc"
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start
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.global mqmachu
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mqmachu:
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set_fr_iimmed 3,2,fr8 ; multiply small numbers
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set_fr_iimmed 2,3,fr10
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set_fr_iimmed 1,2,fr9 ; multiply by 1
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set_fr_iimmed 2,1,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 6,acc0
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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test_accg_immed 0,accg2
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test_acc_immed 2,acc2
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test_accg_immed 0,accg3
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test_acc_immed 2,acc3
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set_fr_iimmed 0,2,fr8 ; multiply by 0
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set_fr_iimmed 2,0,fr10
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set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
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set_fr_iimmed 2,0x3fff,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 6,acc0
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0x0000,0x8000,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0x0000,0x8000,acc3
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set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
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set_fr_iimmed 2,0x4000,fr10
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set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
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set_fr_iimmed 2,0x8000,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x8006,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x8006,acc1
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test_accg_immed 0,accg2
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test_acc_immed 0x00018000,acc2
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test_accg_immed 0,accg3
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test_acc_immed 0x00018000,acc3
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set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
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set_fr_iimmed 0x7fff,0x7fff,fr10
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set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 0x3fff8007,acc0
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test_accg_immed 0,accg1
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test_acc_immed 0x3fff8007,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0x4001,0x8000,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0x4001,0x8000,acc3
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set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
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set_fr_iimmed 0xffff,0xffff,fr10
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set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
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set_fr_iimmed 0xffff,0xffff,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 1,accg0
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test_acc_limmed 0x3ffd,0x8008,acc0
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test_accg_immed 1,accg1
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test_acc_limmed 0x3ffd,0x8008,acc1
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test_accg_immed 1,accg2
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test_acc_limmed 0x3fff,0x8001,acc2
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test_accg_immed 1,accg3
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test_acc_limmed 0x3fff,0x8001,acc3
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set_accg_immed 0xff,accg0 ; saturation
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set_acc_immed 0xffffffff,acc0
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set_accg_immed 0xff,accg1
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set_acc_immed 0xffffffff,acc1
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set_accg_immed 0xff,accg2 ; saturation
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set_acc_immed 0xffffffff,acc2
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set_accg_immed 0xff,accg3
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set_acc_immed 0xffffffff,acc3
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set_fr_iimmed 1,1,fr8
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set_fr_iimmed 1,1,fr10
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set_fr_iimmed 1,1,fr9
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set_fr_iimmed 1,1,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0xffff,acc0
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xffff,acc1
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test_accg_immed 0xff,accg2
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test_acc_limmed 0xffff,0xffff,acc2
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test_accg_immed 0xff,accg3
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test_acc_limmed 0xffff,0xffff,acc3
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set_fr_iimmed 0xffff,0x0000,fr8
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set_fr_iimmed 0xffff,0xffff,fr10
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set_fr_iimmed 0x0000,0xffff,fr9
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set_fr_iimmed 0xffff,0xffff,fr11
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mqmachu fr8,fr10,acc0
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test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0xffff,acc0
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xffff,acc1
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test_accg_immed 0xff,accg2
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test_acc_limmed 0xffff,0xffff,acc2
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test_accg_immed 0xff,accg3
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test_acc_limmed 0xffff,0xffff,acc3
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pass
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