URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [ftieq.cgs] - Blame information for rev 227

Go to most recent revision | Details | Compare with Previous | View Log


# frv testcase for ftieq $FCCi_2,$GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global ftieq
ftieq:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x1 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x2 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x3 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x5 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x6 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_fcc         0x7 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok8,lr
        set_fcc         0x8 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok8:
        set_psr_et      1
        set_spr_addr    ok9,lr
        set_fcc         0x9 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok9:
        set_psr_et      1
        set_spr_addr    oka,lr
        set_fcc         0xa 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_psr_et      1
        set_spr_addr    okb,lr
        set_fcc         0xb 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_psr_et      1
        set_spr_addr    okc,lr
        set_fcc         0xc 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okc:
        set_psr_et      1
        set_spr_addr    okd,lr
        set_fcc         0xd 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okd:
        set_psr_et      1
        set_spr_addr    oke,lr
        set_fcc         0xe 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oke:
        set_psr_et      1
        set_spr_addr    okf,lr
        set_fcc         0xf 0
        ftieq           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	227	jeremybenn	`# frv testcase for ftieq $FCCi_2,$GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global ftieq`
9			`ftieq:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_spr_addr bad,lr`
19			`set_fcc 0x0 0`
20			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
21
22			`set_spr_addr bad,lr`
23			`set_fcc 0x1 0`
24			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
25
26			`set_spr_addr bad,lr`
27			`set_fcc 0x2 0`
28			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
29
30			`set_spr_addr bad,lr`
31			`set_fcc 0x3 0`
32			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
33
34			`set_spr_addr bad,lr`
35			`set_fcc 0x4 0`
36			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
37
38			`set_spr_addr bad,lr`
39			`set_fcc 0x5 0`
40			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
41
42			`set_spr_addr bad,lr`
43			`set_fcc 0x6 0`
44			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
45
46			`set_spr_addr bad,lr`
47			`set_fcc 0x7 0`
48			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
49
50			`set_psr_et 1`
51			`set_spr_addr ok8,lr`
52			`set_fcc 0x8 0`
53			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
54			`fail`
55			`ok8:`
56			`set_psr_et 1`
57			`set_spr_addr ok9,lr`
58			`set_fcc 0x9 0`
59			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
60			`fail`
61			`ok9:`
62			`set_psr_et 1`
63			`set_spr_addr oka,lr`
64			`set_fcc 0xa 0`
65			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
66			`fail`
67			`oka:`
68			`set_psr_et 1`
69			`set_spr_addr okb,lr`
70			`set_fcc 0xb 0`
71			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
72			`fail`
73			`okb:`
74			`set_psr_et 1`
75			`set_spr_addr okc,lr`
76			`set_fcc 0xc 0`
77			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
78			`fail`
79			`okc:`
80			`set_psr_et 1`
81			`set_spr_addr okd,lr`
82			`set_fcc 0xd 0`
83			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
84			`fail`
85			`okd:`
86			`set_psr_et 1`
87			`set_spr_addr oke,lr`
88			`set_fcc 0xe 0`
89			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
90			`fail`
91			`oke:`
92			`set_psr_et 1`
93			`set_spr_addr okf,lr`
94			`set_fcc 0xf 0`
95			`ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
96			`fail`
97			`okf:`
98			`pass`
99			`bad:`
100			`fail`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [ftieq.cgs] - Blame information for rev 227