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jeremybenn |
# frv testcase for mp_exception
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# mach: fr500 fr550 frv
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# xerror:
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# This program no longer assembles because the assembler
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# now detects the unaligned registers. For this reason
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# this test is now marked as "xerror" and prints the
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# expected message "fail"
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.include "testutils.inc"
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start
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.global mp_exception
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mpx:
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.if 1
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fail
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.else
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned
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test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mcmpsh.p fr10,fr11,fcc0 ; no exception
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mcmpsh fr10,fr11,fcc2 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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mmulhs.p fr10,fr11,acc3 ; no exception
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mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmulhu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mmulxhs.p fr10,fr11,acc3 ; no exception
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mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmulxhu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mmachs.p fr10,fr11,acc3 ; no exception
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mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmachu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned
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mqaddhss fr10,fr12,fr14 ; no exception
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr10,fr12,fr14 ; no exception
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mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned
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mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqaddhss fr10,fr12,fr14 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqmulhs.p fr10,fr11,acc3 ; no exception
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mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 144 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 145 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 146 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 151 |
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mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned
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| 152 |
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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| 153 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 154 |
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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| 155 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 156 |
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 159 |
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mqmulhu fr10,fr12,acc0 ; no exception
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| 160 |
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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| 161 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 162 |
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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| 163 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 164 |
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqmulxhs.p fr10,fr11,acc3 ; no exception
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mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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| 171 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 172 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 173 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 174 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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| 175 |
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or_spr_immed 2,msr0 ; Set msr0.ovf
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| 177 |
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or_spr_immed 2,msr1 ; Set msr1.ovf
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| 178 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 179 |
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mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned
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| 180 |
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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| 181 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 182 |
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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| 183 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 184 |
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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| 185 |
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| 186 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 187 |
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mqmulxhu fr10,fr12,acc0 ; no exception
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| 188 |
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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| 189 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 190 |
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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| 191 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 192 |
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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| 193 |
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| 194 |
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set_spr_immed 0,msr0
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| 195 |
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set_spr_immed 0,msr1
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| 196 |
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mqmachs.p fr10,fr12,acc3 ; no exception
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| 197 |
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mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned
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| 198 |
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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| 199 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 200 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 201 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 202 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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| 203 |
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| 204 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 205 |
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mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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| 206 |
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mqmachu fr10,fr12,acc0 ; no exception
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| 207 |
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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| 208 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 209 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 210 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 211 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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| 212 |
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| 213 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 214 |
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mqmachu.p fr10,fr12,acc0 ; no exception
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| 215 |
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mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
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| 216 |
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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| 217 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 218 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 219 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 220 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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| 221 |
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| 222 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 223 |
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mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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| 224 |
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mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
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| 225 |
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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| 226 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 227 |
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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| 228 |
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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| 229 |
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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| 230 |
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| 231 |
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or_spr_immed 2,msr0 ; Set msr0.ovf
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| 232 |
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or_spr_immed 2,msr1 ; Set msr1.ovf
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| 233 |
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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| 234 |
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mqmachu fr10,fr12,acc0 ; no exception
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| 235 |
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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| 236 |
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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| 237 |
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|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 238 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 239 |
|
|
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
|
| 240 |
|
|
|
| 241 |
|
|
set_spr_immed 0,msr0
|
| 242 |
|
|
set_spr_immed 0,msr1
|
| 243 |
|
|
mqcpxrs.p fr10,fr12,acc0 ; no exception
|
| 244 |
|
|
mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned
|
| 245 |
|
|
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
|
| 246 |
|
|
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
|
| 247 |
|
|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 248 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 249 |
|
|
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
|
| 250 |
|
|
|
| 251 |
|
|
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
|
| 252 |
|
|
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
|
| 253 |
|
|
mqcpxru fr10,fr12,acc0 ; no exception
|
| 254 |
|
|
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
|
| 255 |
|
|
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
|
| 256 |
|
|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 257 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 258 |
|
|
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
|
| 259 |
|
|
|
| 260 |
|
|
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
|
| 261 |
|
|
mqcpxru.p fr10,fr12,acc0 ; no exception
|
| 262 |
|
|
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
|
| 263 |
|
|
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
|
| 264 |
|
|
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
|
| 265 |
|
|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 266 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 267 |
|
|
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
|
| 268 |
|
|
|
| 269 |
|
|
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
|
| 270 |
|
|
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
|
| 271 |
|
|
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
|
| 272 |
|
|
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
|
| 273 |
|
|
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
|
| 274 |
|
|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 275 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 276 |
|
|
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
|
| 277 |
|
|
|
| 278 |
|
|
or_spr_immed 2,msr0 ; Set msr0.ovf
|
| 279 |
|
|
or_spr_immed 2,msr1 ; Set msr1.ovf
|
| 280 |
|
|
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
|
| 281 |
|
|
mqcpxru fr10,fr12,acc0 ; no exception
|
| 282 |
|
|
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
|
| 283 |
|
|
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
|
| 284 |
|
|
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
|
| 285 |
|
|
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
|
| 286 |
|
|
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
|
| 287 |
|
|
|
| 288 |
|
|
pass
|
| 289 |
|
|
.endif
|
