OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [interrupts/] [mp_exception.cgs] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
# frv testcase for mp_exception
2 
# mach: fr500 fr550 frv
3 
# xerror:
4 
 
5 
# This program no longer assembles because the assembler
6 
# now detects the unaligned registers. For this reason
7 
# this test is now marked as "xerror" and prints the
8 
# expected message "fail"
9 
 
10 
        .include "testutils.inc"
11 
 
12 
        start
13 
 
14 
        .global mp_exception
15 
mpx:
16 
.if 1
17 
        fail
18 
.else
19 
        or_spr_immed    2,msr0          ; Set msr0.ovf
20 
        or_spr_immed    2,msr1          ; Set msr1.ovf
21 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
22 
        mcmpsh          fr10,fr11,fcc1  ; mp_exception: cr-not-aligned
23 
        test_spr_bits   0x7000,12,3,msr0; msr0.mtt is set
24 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
25 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
26 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
27 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf is set
28 
 
29 
        or_spr_immed    2,msr0          ; Set msr0.ovf
30 
        or_spr_immed    2,msr1          ; Set msr1.ovf
31 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
32 
        mcmpsh.p        fr10,fr11,fcc0  ; no exception
33 
        mcmpsh          fr10,fr11,fcc2  ; no exception
34 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
35 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
36 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
37 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
38 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
39 
 
40 
        mmulhs.p        fr10,fr11,acc3  ; no exception
41 
        mmulhs          fr10,fr11,acc1  ; mp_exception: acc-not-aligned
42 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
43 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
44 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
45 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
46 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
47 
 
48 
        or_spr_immed    2,msr0          ; Set msr0.ovf
49 
        or_spr_immed    2,msr1          ; Set msr1.ovf
50 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
51 
        mmulhu          fr10,fr11,acc0  ; no exception
52 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
53 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
54 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
55 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
56 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
57 
 
58 
        set_spr_immed   0,msr0
59 
        set_spr_immed   0,msr1
60 
        mmulxhs.p       fr10,fr11,acc3  ; no exception
61 
        mmulxhs         fr10,fr11,acc1  ; mp_exception: acc-not-aligned
62 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
63 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
64 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
65 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
66 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
67 
 
68 
        or_spr_immed    2,msr0          ; Set msr0.ovf
69 
        or_spr_immed    2,msr1          ; Set msr1.ovf
70 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
71 
        mmulxhu         fr10,fr11,acc0  ; no exception
72 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
73 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
74 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
75 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
76 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
77 
 
78 
        set_spr_immed   0,msr0
79 
        set_spr_immed   0,msr1
80 
        mmachs.p        fr10,fr11,acc3  ; no exception
81 
        mmachs          fr10,fr11,acc1  ; mp_exception: acc-not-aligned
82 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
83 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
84 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
85 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
86 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
87 
 
88 
        or_spr_immed    2,msr0          ; Set msr0.ovf
89 
        or_spr_immed    2,msr1          ; Set msr1.ovf
90 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
91 
        mmachu          fr10,fr11,acc0  ; no exception
92 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
93 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
94 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
95 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
96 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
97 
 
98 
        set_spr_immed   0,msr0
99 
        set_spr_immed   0,msr1
100 
        mqaddhss.p      fr10,fr12,fr17  ; mp_exception: register-not-aligned
101 
        mqaddhss        fr10,fr12,fr14  ; no exception
102 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
103 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
104 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
105 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
106 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
107 
 
108 
        set_spr_immed   0,msr0
109 
        set_spr_immed   0,msr1
110 
        mqaddhss.p      fr10,fr12,fr14  ; no exception
111 
        mqaddhss        fr10,fr13,fr16  ; mp_exception: register-not-aligned
112 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
113 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
114 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
115 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
116 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
117 
 
118 
        set_spr_immed   0,msr0
119 
        set_spr_immed   0,msr1
120 
        mqaddhss.p      fr19,fr12,fr14  ; mp_exception: register-not-aligned
121 
        mqaddhss        fr10,fr13,fr16  ; mp_exception: register-not-aligned
122 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
123 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
124 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
125 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
126 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
127 
 
128 
        or_spr_immed    2,msr0          ; Set msr0.ovf
129 
        or_spr_immed    2,msr1          ; Set msr1.ovf
130 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
131 
        mqaddhss        fr10,fr12,fr14  ; no exception
132 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
133 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
134 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
135 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
136 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
137 
 
138 
        set_spr_immed   0,msr0
139 
        set_spr_immed   0,msr1
140 
        mqmulhs.p       fr10,fr11,acc3  ; no exception
141 
        mqmulhs         fr10,fr11,acc2  ; mp_exception: acc-not-aligned
142 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
143 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
144 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
145 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
146 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
147 
 
148 
        or_spr_immed    2,msr0          ; Set msr0.ovf
149 
        or_spr_immed    2,msr1          ; Set msr1.ovf
150 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
151 
        mqmulhu         fr10,fr11,acc0  ; mp_exception: register_not_aligned
152 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
153 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
154 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
155 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
156 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
157 
 
158 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
159 
        mqmulhu         fr10,fr12,acc0  ; no exception
160 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
161 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
162 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
163 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
164 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
165 
 
166 
        set_spr_immed   0,msr0
167 
        set_spr_immed   0,msr1
168 
        mqmulxhs.p      fr10,fr11,acc3  ; no exception
169 
        mqmulxhs        fr10,fr11,acc2  ; mp_exception: acc-not-aligned
170 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
171 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
172 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
173 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
174 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
175 
 
176 
        or_spr_immed    2,msr0          ; Set msr0.ovf
177 
        or_spr_immed    2,msr1          ; Set msr1.ovf
178 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
179 
        mqmulxhu        fr10,fr11,acc0  ; mp_exception: register-not-aligned
180 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
181 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
182 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
183 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
184 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
185 
 
186 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
187 
        mqmulxhu        fr10,fr12,acc0  ; no exception
188 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
189 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
190 
        test_spr_bits   0x0002,1,1,msr0 ; msr0.ovf is still set
191 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
192 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
193 
 
194 
        set_spr_immed   0,msr0
195 
        set_spr_immed   0,msr1
196 
        mqmachs.p       fr10,fr12,acc3  ; no exception
197 
        mqmachs         fr10,fr12,acc2  ; mp_exception: acc-not-aligned
198 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
199 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
200 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
201 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
202 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
203 
 
204 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
205 
        mqmachu.p       fr19,fr12,acc0  ; mp_exception: register-not-aligned
206 
        mqmachu         fr10,fr12,acc0  ; no exception
207 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
208 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
209 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
210 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
211 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
212 
 
213 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
214 
        mqmachu.p       fr10,fr12,acc0  ; no exception
215 
        mqmachu         fr19,fr12,acc0  ; mp_exception: register-not-aligned
216 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
217 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
218 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
219 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
220 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
221 
 
222 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
223 
        mqmachu.p       fr19,fr12,acc0  ; mp_exception: register-not-aligned
224 
        mqmachu         fr19,fr12,acc0  ; mp_exception: register-not-aligned
225 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
226 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
227 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
228 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
229 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
230 
 
231 
        or_spr_immed    2,msr0          ; Set msr0.ovf
232 
        or_spr_immed    2,msr1          ; Set msr1.ovf
233 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
234 
        mqmachu         fr10,fr12,acc0  ; no exception
235 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
236 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
237 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
238 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
239 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
240 
 
241 
        set_spr_immed   0,msr0
242 
        set_spr_immed   0,msr1
243 
        mqcpxrs.p       fr10,fr12,acc0  ; no exception
244 
        mqcpxrs         fr10,fr12,acc1  ; mp_exception: acc-not-aligned
245 
        test_spr_bits   0x7000,12,2,msr0; msr0.mtt is set
246 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
247 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
248 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
249 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
250 
 
251 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
252 
        mqcpxru.p       fr19,fr12,acc0  ; mp_exception: register-not-aligned
253 
        mqcpxru         fr10,fr12,acc0  ; no exception
254 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
255 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
256 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
257 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
258 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
259 
 
260 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
261 
        mqcpxru.p       fr10,fr12,acc0  ; no exception
262 
        mqcpxru         fr19,fr12,acc0  ; mp_exception: register-not-aligned
263 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
264 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
265 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
266 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
267 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
268 
 
269 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
270 
        mqcpxru.p       fr19,fr12,acc0  ; mp_exception: register-not-aligned
271 
        mqcpxru         fr19,fr12,acc0  ; mp_exception: register-not-aligned
272 
        test_spr_bits   0x7000,12,6,msr0; msr0.mtt is set
273 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
274 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
275 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
276 
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
277 
 
278 
        or_spr_immed    2,msr0          ; Set msr0.ovf
279 
        or_spr_immed    2,msr1          ; Set msr1.ovf
280 
        and_spr_immed   0xffff8fff,msr0 ; Clear msr0.mtt
281 
        mqcpxru         fr10,fr12,acc0  ; no exception
282 
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
283 
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
284 
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
285 
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
286 
        test_spr_bits   0x0002,1,1,msr1 ; msr1.ovf still set
287 
 
288 
        pass
289 
.endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.