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# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global srlicc
srlicc:
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x05,0          ; Set mask opposite of expected
        srlicc          gr8,0x1e0,gr8,icc0      ; Shift by 0
        test_icc        1 0 0 0 icc0
        test_gr_limmed  0x8000,0x0000,gr8
 
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x0f,0          ; Set mask opposite of expected
        srlicc          gr8,-31,gr8,icc0        ; Shift by 1
        test_icc        0 0 1 0 icc0
        test_gr_limmed  0x4000,0x0000,gr8
 
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x0f,0          ; Set mask opposite of expected
        srlicc          gr8,31,gr8,icc0 ; Shift by 31
        test_icc        0 0 1 0 icc0
        test_gr_immed   1,gr8
 
        set_gr_limmed   0x4000,0x0000,gr8
        set_icc         0x0a,0          ; Set mask opposite of expected
        srlicc          gr8,31,gr8,icc0 ; clear register
        test_icc        0 1 1 1 icc0
        test_gr_immed   0x00000000,gr8
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global srlicc`
9			`srlicc:`
10			`set_gr_limmed 0x8000,0x0000,gr8`
11			`set_icc 0x05,0 ; Set mask opposite of expected`
12			`srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0`
13			`test_icc 1 0 0 0 icc0`
14			`test_gr_limmed 0x8000,0x0000,gr8`
15
16			`set_gr_limmed 0x8000,0x0000,gr8`
17			`set_icc 0x0f,0 ; Set mask opposite of expected`
18			`srlicc gr8,-31,gr8,icc0 ; Shift by 1`
19			`test_icc 0 0 1 0 icc0`
20			`test_gr_limmed 0x4000,0x0000,gr8`
21
22			`set_gr_limmed 0x8000,0x0000,gr8`
23			`set_icc 0x0f,0 ; Set mask opposite of expected`
24			`srlicc gr8,31,gr8,icc0 ; Shift by 31`
25			`test_icc 0 0 1 0 icc0`
26			`test_gr_immed 1,gr8`
27
28			`set_gr_limmed 0x4000,0x0000,gr8`
29			`set_icc 0x0a,0 ; Set mask opposite of expected`
30			`srlicc gr8,31,gr8,icc0 ; clear register`
31			`test_icc 0 1 1 1 icc0`
32			`test_gr_immed 0x00000000,gr8`
33
34			`pass`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [srlicc.cgs] - Blame information for rev 856