URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [h8300/] [adds.s] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log


# Hitachi H8 testcase 'adds'
# mach(): h8300h h8300s h8sx
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        # Instructions tested:
        # adds #1, erd          ; 0 b 0 xerd
        # adds #2, erd          ; 0 b 8 xerd
        # adds #4, erd          ; 0 b 9 xerd
        #
 
        start
.if (sim_cpu)                   ; 32 bit only
adds_1:
        set_grs_a5a5
        set_ccr_zero
 
        adds    #1, er0
 
        test_cc_clear           ; adds should not affect any condition codes
        test_h_gr32  0xa5a5a5a6 er0     ; result of adds #1
 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
adds_2:
        set_grs_a5a5
        set_ccr_zero
 
        adds    #2, er0
 
        test_cc_clear           ; adds should not affect any condition codes
        test_h_gr32  0xa5a5a5a7 er0     ; result of adds #2
 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
adds_4:
        set_grs_a5a5
        set_ccr_zero
 
        adds    #4, er0
 
        test_cc_clear           ; adds should not affect any condition codes
        test_h_gr32  0xa5a5a5a9 er0     ; result of adds #4
 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        pass
.endif
        exit 0

Line No.	Rev	Author	Line
1	227	jeremybenn	`# Hitachi H8 testcase 'adds'`
2			`# mach(): h8300h h8300s h8sx`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`# Instructions tested:`
14			`# adds #1, erd ; 0 b 0 xerd`
15			`# adds #2, erd ; 0 b 8 xerd`
16			`# adds #4, erd ; 0 b 9 xerd`
17			`#`
18
19			`start`
20			`.if (sim_cpu) ; 32 bit only`
21			`adds_1:`
22			`set_grs_a5a5`
23			`set_ccr_zero`
24
25			`adds #1, er0`
26
27			`test_cc_clear ; adds should not affect any condition codes`
28			`test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1`
29
30			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
31			`test_gr_a5a5 2`
32			`test_gr_a5a5 3`
33			`test_gr_a5a5 4`
34			`test_gr_a5a5 5`
35			`test_gr_a5a5 6`
36			`test_gr_a5a5 7`
37
38			`adds_2:`
39			`set_grs_a5a5`
40			`set_ccr_zero`
41
42			`adds #2, er0`
43
44			`test_cc_clear ; adds should not affect any condition codes`
45			`test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2`
46
47			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
48			`test_gr_a5a5 2`
49			`test_gr_a5a5 3`
50			`test_gr_a5a5 4`
51			`test_gr_a5a5 5`
52			`test_gr_a5a5 6`
53			`test_gr_a5a5 7`
54
55			`adds_4:`
56			`set_grs_a5a5`
57			`set_ccr_zero`
58
59			`adds #4, er0`
60
61			`test_cc_clear ; adds should not affect any condition codes`
62			`test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4`
63
64			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
65			`test_gr_a5a5 2`
66			`test_gr_a5a5 3`
67			`test_gr_a5a5 4`
68			`test_gr_a5a5 5`
69			`test_gr_a5a5 6`
70			`test_gr_a5a5 7`
71
72			`pass`
73			`.endif`
74			`exit 0`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [h8300/] [adds.s] - Blame information for rev 816