OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [addx.cgs] - Blame information for rev 828

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# m32r testcase for addx $dr,$sr
2
# mach(): m32r m32rx
3
# timeout(): 42
4
 
5
# timeout is set to test it
6
 
7
        .include "testutils.inc"
8
 
9
        start
10
 
11
        .global addx
12
addx:
13
        mvi_h_condbit 1
14
        mvi_h_gr r4, 1
15
        mvi_h_gr r5, 2
16
        addx r4, r5
17
        bc not_ok
18
        test_h_gr r4, 4
19
 
20
        mvi_h_gr r4, 0xfffffffe
21
        addx r4, r5
22
        bnc not_ok
23
        test_h_gr r4, 0
24
 
25
        mvi_h_gr r4, -1
26
        mvi_h_gr r5, -1
27
        mvi_h_condbit 1
28
        addx r4,r5
29
        bnc not_ok
30
        test_h_gr r4, -1
31
 
32
        mvi_h_gr r4,-1
33
        mvi_h_gr r5,0x7fffffff
34
        mvi_h_condbit 1
35
        addx r5,r4
36
        bnc not_ok
37
        test_h_gr r5,0x7fffffff
38
 
39
        pass
40
 
41
not_ok:
42
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.