OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [cmpu.cgs] - Blame information for rev 828

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# m32r testcase for cmpu $src1,$src2
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global cmpu
9
cmpu:
10
        mvi_h_condbit 0
11
        mvi_h_gr r4, 1
12
        mvi_h_gr r5, -2
13
        cmpu r4, r5
14
        bc ok
15
not_ok:
16
        fail
17
ok:
18
        mvi_h_condbit 1
19
        mvi_h_gr r4, -1
20
        cmpu r4, r5
21
        bc not_ok
22
 
23
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.