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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [fabs.s] - Blame information for rev 816

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Line No. Rev Author Line
1 227 jeremybenn
# sh testcase for fabs
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# mach: sh
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# as(sh):       -defsym sim_cpu=0
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        .include "testutils.inc"
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        start
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fabs_freg_b0:
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        single_prec
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        bank0
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        set_grs_a5a5
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        set_fprs_a5a5
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        # fabs(0.0) = 0.0.
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        fldi0   fr0
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        fabs    fr0
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        fldi0   fr1
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        fcmp/eq fr0, fr1
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        bt      .L1
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        fail
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.L1:
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        # fabs(1.0) = 1.0.
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        fldi1   fr0
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        fabs    fr0
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        fldi1   fr1
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        fcmp/eq fr0, fr1
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        bt      .L2
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        fail
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.L2:
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        # fabs(-1.0) = 1.0.
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        fldi1   fr0
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        fneg    fr0
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        fabs    fr0
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        fldi1   fr1
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        fcmp/eq fr0, fr1
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        bt      .L3
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        fail
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.L3:
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        test_grs_a5a5
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        test_fpr_a5a5 fr2
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        test_fpr_a5a5 fr3
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        test_fpr_a5a5 fr4
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        test_fpr_a5a5 fr5
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        test_fpr_a5a5 fr6
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        test_fpr_a5a5 fr7
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        test_fpr_a5a5 fr8
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        test_fpr_a5a5 fr9
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        test_fpr_a5a5 fr10
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        test_fpr_a5a5 fr11
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        test_fpr_a5a5 fr12
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        test_fpr_a5a5 fr13
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        test_fpr_a5a5 fr14
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        test_fpr_a5a5 fr15
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fabs_dreg_b0:
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        # double precision tests.
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        set_grs_a5a5
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        set_fprs_a5a5
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        double_prec
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        # fabs(0.0) = 0.0.
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        fldi0   fr0
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        flds    fr0, fpul
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        fcnvsd  fpul, dr0
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        fabs dr0
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        assert_dpreg_i 0 dr0
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        # fabs(1.0) = 1.0.
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        fldi1   fr0
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        flds    fr0, fpul
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        fcnvsd  fpul, dr0
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        fabs dr0
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        assert_dpreg_i 1 dr0
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        # check.
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        fldi1 fr2
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        flds    fr2, fpul
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        fcnvsd  fpul, dr2
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        fcmp/eq dr0, dr2
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        bt      .L4
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        fail
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.L4:
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        # fabs(-1.0) = 1.0.
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        fldi1 fr0
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        fneg fr0
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        flds    fr0, fpul
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        fcnvsd  fpul, dr0
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        fabs dr0
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        assert_dpreg_i 1 dr0
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        # check.
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        fldi1 fr2
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        flds    fr2, fpul
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        fcnvsd  fpul, dr2
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        fcmp/eq dr0, dr2
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        bt      .L5
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        fail
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.L5:
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        test_grs_a5a5
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        assert_dpreg_i 1 dr0
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        assert_dpreg_i 1 dr2
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        test_fpr_a5a5 fr4
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        test_fpr_a5a5 fr5
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        test_fpr_a5a5 fr6
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        test_fpr_a5a5 fr7
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        test_fpr_a5a5 fr8
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        test_fpr_a5a5 fr9
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        test_fpr_a5a5 fr10
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        test_fpr_a5a5 fr11
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        test_fpr_a5a5 fr12
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        test_fpr_a5a5 fr13
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        test_fpr_a5a5 fr14
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        test_fpr_a5a5 fr15
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        pass
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        exit 0

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