URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [fschg.s] - Blame information for rev 842

Details | Compare with Previous | View Log


# sh testcase for fschg
# mach: sh
# as(sh):       -defsym sim_cpu=0
 
        .include "testutils.inc"
 
        start
        set_grs_a5a5
        set_fprs_a5a5
        sts     fpscr, r0
        assertreg0      0
        fschg
        sts     fpscr, r0
        assertreg0      0x100000
        fschg
        sts     fpscr, r0
        assertreg0      0
        fschg
        sts     fpscr, r0
        assertreg0      0x100000
        fschg
        sts     fpscr, r0
        assertreg0      0
 
        set_greg 0xa5a5a5a5 r0
        test_grs_a5a5
        test_fprs_a5a5
        pass
        exit 0

Line No.	Rev	Author	Line
1	227	jeremybenn	`# sh testcase for fschg`
2			`# mach: sh`
3			`# as(sh): -defsym sim_cpu=0`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`set_grs_a5a5`
9			`set_fprs_a5a5`
10			`sts fpscr, r0`
11			`assertreg0 0`
12			`fschg`
13			`sts fpscr, r0`
14			`assertreg0 0x100000`
15			`fschg`
16			`sts fpscr, r0`
17			`assertreg0 0`
18			`fschg`
19			`sts fpscr, r0`
20			`assertreg0 0x100000`
21			`fschg`
22			`sts fpscr, r0`
23			`assertreg0 0`
24
25			`set_greg 0xa5a5a5a5 r0`
26			`test_grs_a5a5`
27			`test_fprs_a5a5`
28			`pass`
29			`exit 0`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [fschg.s] - Blame information for rev 842