URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [ldrc.s] - Blame information for rev 842

Details | Compare with Previous | View Log


# sh testcase for ldrc, strc
# mach: shdsp
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
 
setrc_imm:
        set_grs_a5a5
        # Test setrc
        #
        ldrs    lstart
        ldre    lend
        setrc   #0xff
        get_sr  r1
        shlr16  r1
        set_greg 0xfff, r0
        and     r0, r1
        assertreg 0xff, r1
 
        stc     rs, r0  ! rs unchanged
        assertreg0      lstart
        stc     re, r0  ! re unchanged
        assertreg0      lend
 
        set_greg 0xa5a5a5a5, r0
        set_greg 0xa5a5a5a5, r1
 
        test_grs_a5a5
 
setrc_reg:
        set_grs_a5a5
        # Test setrc
        #
        ldrs    lstart
        ldre    lend
        set_greg        0xfff, r0
        setrc   r0
        get_sr  r1
        shlr16  r1
        set_greg 0xfff, r0
        and     r0, r1
        assertreg 0xfff, r1
 
        stc     rs, r0  ! rs unchanged
        assertreg0      lstart
        stc     re, r0  ! re unchanged
        assertreg0      lend
 
        set_greg 0xa5a5a5a5, r0
        set_greg 0xa5a5a5a5, r1
 
        test_grs_a5a5
 
        bra     ldrc_imm
 
        .global lstart
        .align 2
lstart: nop
        nop
        nop
        nop
        .global lend
        .align 2
lend:   nop
        nop
        nop
        nop
 
ldrc_imm:
        set_grs_a5a5
        # Test ldrc
        setrc   #0x0    ! zero rc
        ldrc    #0xa5
        get_sr  r1
        shlr16  r1
        set_greg 0xfff, r0
        and     r0, r1
        assertreg 0xa5, r1
        stc     rs, r0  ! rs unchanged
        assertreg0      lstart
        stc     re, r0
        assertreg0      lend+1  ! bit 0 set in re
 
        # fix up re for next test
        dt      r0      ! Ugh!  No DEC insn!
        ldc     r0, re
 
        set_greg 0xa5a5a5a5, r0
        set_greg 0xa5a5a5a5, r1
 
        test_grs_a5a5
 
ldrc_reg:
        set_grs_a5a5
        # Test ldrc
        setrc   #0x0    ! zero rc
        set_greg 0xa5a, r0
        ldrc    r0
        get_sr  r1
        shlr16  r1
        set_greg 0xfff, r0
        and     r0, r1
        assertreg 0xa5a, r1
        stc     rs, r0  ! rs unchanged
        assertreg0      lstart
        stc     re, r0
        assertreg0      lend+1  ! bit 0 set in re
 
        set_greg 0xa5a5a5a5, r0
        set_greg 0xa5a5a5a5, r1
 
        test_grs_a5a5
 
        pass
        exit 0
 

Line No.	Rev	Author	Line
1	227	jeremybenn	`# sh testcase for ldrc, strc`
2			`# mach: shdsp`
3			`# as(shdsp): -defsym sim_cpu=1 -dsp`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`setrc_imm:`
10			`set_grs_a5a5`
11			`# Test setrc`
12			`#`
13			`ldrs lstart`
14			`ldre lend`
15			`setrc #0xff`
16			`get_sr r1`
17			`shlr16 r1`
18			`set_greg 0xfff, r0`
19			`and r0, r1`
20			`assertreg 0xff, r1`
21
22			`stc rs, r0 ! rs unchanged`
23			`assertreg0 lstart`
24			`stc re, r0 ! re unchanged`
25			`assertreg0 lend`
26
27			`set_greg 0xa5a5a5a5, r0`
28			`set_greg 0xa5a5a5a5, r1`
29
30			`test_grs_a5a5`
31
32			`setrc_reg:`
33			`set_grs_a5a5`
34			`# Test setrc`
35			`#`
36			`ldrs lstart`
37			`ldre lend`
38			`set_greg 0xfff, r0`
39			`setrc r0`
40			`get_sr r1`
41			`shlr16 r1`
42			`set_greg 0xfff, r0`
43			`and r0, r1`
44			`assertreg 0xfff, r1`
45
46			`stc rs, r0 ! rs unchanged`
47			`assertreg0 lstart`
48			`stc re, r0 ! re unchanged`
49			`assertreg0 lend`
50
51			`set_greg 0xa5a5a5a5, r0`
52			`set_greg 0xa5a5a5a5, r1`
53
54			`test_grs_a5a5`
55
56			`bra ldrc_imm`
57
58			`.global lstart`
59			`.align 2`
60			`lstart: nop`
61			`nop`
62			`nop`
63			`nop`
64			`.global lend`
65			`.align 2`
66			`lend: nop`
67			`nop`
68			`nop`
69			`nop`
70
71			`ldrc_imm:`
72			`set_grs_a5a5`
73			`# Test ldrc`
74			`setrc #0x0 ! zero rc`
75			`ldrc #0xa5`
76			`get_sr r1`
77			`shlr16 r1`
78			`set_greg 0xfff, r0`
79			`and r0, r1`
80			`assertreg 0xa5, r1`
81			`stc rs, r0 ! rs unchanged`
82			`assertreg0 lstart`
83			`stc re, r0`
84			`assertreg0 lend+1 ! bit 0 set in re`
85
86			`# fix up re for next test`
87			`dt r0 ! Ugh! No DEC insn!`
88			`ldc r0, re`
89
90			`set_greg 0xa5a5a5a5, r0`
91			`set_greg 0xa5a5a5a5, r1`
92
93			`test_grs_a5a5`
94
95			`ldrc_reg:`
96			`set_grs_a5a5`
97			`# Test ldrc`
98			`setrc #0x0 ! zero rc`
99			`set_greg 0xa5a, r0`
100			`ldrc r0`
101			`get_sr r1`
102			`shlr16 r1`
103			`set_greg 0xfff, r0`
104			`and r0, r1`
105			`assertreg 0xa5a, r1`
106			`stc rs, r0 ! rs unchanged`
107			`assertreg0 lstart`
108			`stc re, r0`
109			`assertreg0 lend+1 ! bit 0 set in re`
110
111			`set_greg 0xa5a5a5a5, r0`
112			`set_greg 0xa5a5a5a5, r1`
113
114			`test_grs_a5a5`
115
116			`pass`
117			`exit 0`
118

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [ldrc.s] - Blame information for rev 842