OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [pshai.s] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# sh testcase for psha <imm>
2
# mach: all
3
# as(sh):       -defsym sim_cpu=0
4
# as(shdsp):    -defsym sim_cpu=1 -dsp
5
 
6
        .include "testutils.inc"
7
 
8
        start
9
 
10
psha_imm:                       ! shift arithmetic, immediate operand
11
        set_grs_a5a5
12
        lds     r0, a0
13
        pcopy   a0, a1
14
        lds     r0, x0
15
        lds     r0, x1
16
        lds     r0, y0
17
        lds     r0, y1
18
        pcopy   x0, m0
19
        pcopy   y1, m1
20
 
21
        set_sreg 0x1, a0
22
        psha    #0, a0
23
        assert_sreg     0x1, a0
24
        psha    #-0, a0
25
        assert_sreg     0x1, a0
26
 
27
        psha    #1, a0
28
        assert_sreg     0x2, a0
29
        psha    #-1, a0
30
        assert_sreg     0x1, a0
31
 
32
        psha    #2, a0
33
        assert_sreg     0x4, a0
34
        psha    #-2, a0
35
        assert_sreg     0x1, a0
36
 
37
        psha    #3, a0
38
        assert_sreg     0x8, a0
39
        psha    #-3, a0
40
        assert_sreg     0x1, a0
41
 
42
        psha    #4, a0
43
        assert_sreg     0x10, a0
44
        psha    #-4, a0
45
        assert_sreg     0x1, a0
46
 
47
        psha    #5, a0
48
        assert_sreg     0x20, a0
49
        psha    #-5, a0
50
        assert_sreg     0x1, a0
51
 
52
        psha    #6, a0
53
        assert_sreg     0x40, a0
54
        psha    #-6, a0
55
        assert_sreg     0x1, a0
56
 
57
        psha    #7, a0
58
        assert_sreg     0x80, a0
59
        psha    #-7, a0
60
        assert_sreg     0x1, a0
61
 
62
        psha    #8, a0
63
        assert_sreg     0x100, a0
64
        psha    #-8, a0
65
        assert_sreg     0x1, a0
66
 
67
        psha    #9, a0
68
        assert_sreg     0x200, a0
69
        psha    #-9, a0
70
        assert_sreg     0x1, a0
71
 
72
        psha    #10, a0
73
        assert_sreg     0x400, a0
74
        psha    #-10, a0
75
        assert_sreg     0x1, a0
76
 
77
        psha    #11, a0
78
        assert_sreg     0x800, a0
79
        psha    #-11, a0
80
        assert_sreg     0x1, a0
81
 
82
        psha    #12, a0
83
        assert_sreg     0x1000, a0
84
        psha    #-12, a0
85
        assert_sreg     0x1, a0
86
 
87
        psha    #13, a0
88
        assert_sreg     0x2000, a0
89
        psha    #-13, a0
90
        assert_sreg     0x1, a0
91
 
92
        psha    #14, a0
93
        assert_sreg     0x4000, a0
94
        psha    #-14, a0
95
        assert_sreg     0x1, a0
96
 
97
        psha    #15, a0
98
        assert_sreg     0x8000, a0
99
        psha    #-15, a0
100
        assert_sreg     0x1, a0
101
 
102
        psha    #16, a0
103
        assert_sreg     0x10000, a0
104
        psha    #-16, a0
105
        assert_sreg     0x1, a0
106
 
107
        psha    #17, a0
108
        assert_sreg     0x20000, a0
109
        psha    #-17, a0
110
        assert_sreg     0x1, a0
111
 
112
        psha    #18, a0
113
        assert_sreg     0x40000, a0
114
        psha    #-18, a0
115
        assert_sreg     0x1, a0
116
 
117
        psha    #19, a0
118
        assert_sreg     0x80000, a0
119
        psha    #-19, a0
120
        assert_sreg     0x1, a0
121
 
122
        psha    #20, a0
123
        assert_sreg     0x100000, a0
124
        psha    #-20, a0
125
        assert_sreg     0x1, a0
126
 
127
        psha    #21, a0
128
        assert_sreg     0x200000, a0
129
        psha    #-21, a0
130
        assert_sreg     0x1, a0
131
 
132
        psha    #22, a0
133
        assert_sreg     0x400000, a0
134
        psha    #-22, a0
135
        assert_sreg     0x1, a0
136
 
137
        psha    #23, a0
138
        assert_sreg     0x800000, a0
139
        psha    #-23, a0
140
        assert_sreg     0x1, a0
141
 
142
        psha    #24, a0
143
        assert_sreg     0x1000000, a0
144
        psha    #-24, a0
145
        assert_sreg     0x1, a0
146
 
147
        psha    #25, a0
148
        assert_sreg     0x2000000, a0
149
        psha    #-25, a0
150
        assert_sreg     0x1, a0
151
 
152
        psha    #26, a0
153
        assert_sreg     0x4000000, a0
154
        psha    #-26, a0
155
        assert_sreg     0x1, a0
156
 
157
        psha    #27, a0
158
        assert_sreg     0x8000000, a0
159
        psha    #-27, a0
160
        assert_sreg     0x1, a0
161
 
162
        psha    #28, a0
163
        assert_sreg     0x10000000, a0
164
        psha    #-28, a0
165
        assert_sreg     0x1, a0
166
 
167
        psha    #29, a0
168
        assert_sreg     0x20000000, a0
169
        psha    #-29, a0
170
        assert_sreg     0x1, a0
171
 
172
        psha    #30, a0
173
        assert_sreg     0x40000000, a0
174
        psha    #-30, a0
175
        assert_sreg     0x1, a0
176
 
177
        psha    #31, a0
178
        assert_sreg     0x80000000, a0
179
        psha    #-31, a0
180
        assert_sreg     0xffffffff, a0
181
 
182
        psha    #32, a0
183
        assert_sreg     0x00000000, a0
184
#       I don't grok what should happen here...
185
#       psha    #-32, a0
186
#       assert_sreg     0x0, a0
187
 
188
        test_grs_a5a5
189
        assert_sreg2    0xa5a5a5a5, a1
190
        assert_sreg     0xa5a5a5a5, x0
191
        assert_sreg     0xa5a5a5a5, x1
192
        assert_sreg     0xa5a5a5a5, y0
193
        assert_sreg     0xa5a5a5a5, y1
194
        assert_sreg2    0xa5a5a5a5, m0
195
        assert_sreg2    0xa5a5a5a5, m1
196
 
197
 
198
        pass
199
        exit 0
200
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.