OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [pshli.s] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# sh testcase for pshl <imm>
2
# mach: all
3
# as(sh):       -defsym sim_cpu=0
4
# as(shdsp):    -defsym sim_cpu=1 -dsp
5
 
6
        .include "testutils.inc"
7
 
8
        start
9
 
10
pshl_imm:                       ! shift logical, immediate operand
11
        set_grs_a5a5
12
        lds     r0, a0
13
        pcopy   a0, a1
14
        lds     r0, x0
15
        lds     r0, x1
16
        lds     r0, y0
17
        lds     r0, y1
18
        pcopy   x0, m0
19
        pcopy   y1, m1
20
 
21
        set_sreg 0x10000, a0
22
        pshl    #0, a0
23
        assert_sreg     0x10000, a0
24
        pshl    #-0, a0
25
        assert_sreg     0x10000, a0
26
 
27
        pshl    #1, a0
28
        assert_sreg     0x20000, a0
29
        pshl    #-1, a0
30
        assert_sreg     0x10000, a0
31
 
32
        pshl    #2, a0
33
        assert_sreg     0x40000, a0
34
        pshl    #-2, a0
35
        assert_sreg     0x10000, a0
36
 
37
        pshl    #3, a0
38
        assert_sreg     0x80000, a0
39
        pshl    #-3, a0
40
        assert_sreg     0x10000, a0
41
 
42
        pshl    #4, a0
43
        assert_sreg     0x100000, a0
44
        pshl    #-4, a0
45
        assert_sreg     0x10000, a0
46
 
47
        pshl    #5, a0
48
        assert_sreg     0x200000, a0
49
        pshl    #-5, a0
50
        assert_sreg     0x10000, a0
51
 
52
        pshl    #6, a0
53
        assert_sreg     0x400000, a0
54
        pshl    #-6, a0
55
        assert_sreg     0x10000, a0
56
 
57
        pshl    #7, a0
58
        assert_sreg     0x800000, a0
59
        pshl    #-7, a0
60
        assert_sreg     0x10000, a0
61
 
62
        pshl    #8, a0
63
        assert_sreg     0x1000000, a0
64
        pshl    #-8, a0
65
        assert_sreg     0x10000, a0
66
 
67
        pshl    #9, a0
68
        assert_sreg     0x2000000, a0
69
        pshl    #-9, a0
70
        assert_sreg     0x10000, a0
71
 
72
        pshl    #10, a0
73
        assert_sreg     0x4000000, a0
74
        pshl    #-10, a0
75
        assert_sreg     0x10000, a0
76
 
77
        pshl    #11, a0
78
        assert_sreg     0x8000000, a0
79
        pshl    #-11, a0
80
        assert_sreg     0x10000, a0
81
 
82
        pshl    #12, a0
83
        assert_sreg     0x10000000, a0
84
        pshl    #-12, a0
85
        assert_sreg     0x10000, a0
86
 
87
        pshl    #13, a0
88
        assert_sreg     0x20000000, a0
89
        pshl    #-13, a0
90
        assert_sreg     0x10000, a0
91
 
92
        pshl    #14, a0
93
        assert_sreg     0x40000000, a0
94
        pshl    #-14, a0
95
        assert_sreg     0x10000, a0
96
 
97
        pshl    #15, a0
98
        assert_sreg     0x80000000, a0
99
        pshl    #-15, a0
100
        assert_sreg     0x10000, a0
101
 
102
        pshl    #16, a0
103
        assert_sreg     0x00000000, a0
104
        pshl    #-16, a0
105
        assert_sreg     0x0, a0
106
 
107
        test_grs_a5a5
108
        assert_sreg2    0xa5a5a5a5, a1
109
        assert_sreg     0xa5a5a5a5, x0
110
        assert_sreg     0xa5a5a5a5, x1
111
        assert_sreg     0xa5a5a5a5, y0
112
        assert_sreg     0xa5a5a5a5, y1
113
        assert_sreg2    0xa5a5a5a5, m0
114
        assert_sreg2    0xa5a5a5a5, m1
115
 
116
 
117
        pass
118
        exit 0
119
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.